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Does T-topology achieve 4GByte DDR3 configuration with i.MX6Q?

Question asked by nahoko on Aug 21, 2013
Latest reply on Aug 25, 2013 by nahoko



I am trying to implement 4GB DDR3 for i.MX6Q. Depending on the Hardware Development Guide, T topology design is limited to 4 DDR chips.


> -your design is limited to 4 DDR chips.

> -DDR3, 2GByte using latest memories (4GBytes coming)  (<- Is this really "Byte" ? or "2Gbit / chip"?)


Does it mean that only Fly-by topology can achieve 4GByte configuration?

AW designer says that it's hard to achieve the layout requirement of Fly-by topology with 8 of DDR3 chips and they want to use T-topology.


Thank you.