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IPU/VPU cacheable memory access

Question asked by ofer.livny on Aug 11, 2013
Latest reply on Aug 13, 2013 by ofer.livny
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Hi

 

I'm using iMX6Q, with freescale's linux 3.0.35, and my application is using the IPU and VPU intensively.

I have few processes which process the output of the IPU at the same time.

 

I noticed that my code runs a lot faster when the input is an image which is stored in regular memory (i.e. loaded from file), and slower when the image is in the IPU buffer (dma memory).

 

My guess is that the IPU buffers are not cached in the cpu's caches, which makes the memory access a lot slower.

 

While looking for a solution, I found the IMX6Q_GPR4_IPU_WR_CACHE_CTL / IMX6Q_GPR4_IPU_RD_CACHE_CTL bits in the reference manual.

However, these are not explained well in the documentation I have.

 

Is there a document somewhere explaining what these controls do?

If this bits can help me, is there a patch to freescale's linux that can help me control them (and set this memory to be cacheable) ?

 

Thanks,

Ofer

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