Could you tell - is each CPU core has it's own MMU or all cores has common MMU?
Is it possible to setup MMU table next way:
- CPU0 has full access memory region and read only memory region,
- CPU1 has full access memory region and write only memory region.
Read only [CPU0]/write only[CPU1] are intersected in memory map to implement inter-core communication.
Do you have code example to setup MMU on CPU1-3 (if is it possible) and sets different permissions to DDR3 memory access?