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i.mx6q/i.mx6d

Question asked by Alexander Buraga on Aug 11, 2013
Latest reply on Nov 18, 2013 by Anson Huang

Could you tell - is each CPU core has it's own MMU or all cores has common MMU?

 

Is it possible to setup MMU table next way:

- CPU0 has full access memory region and read only memory region,

- CPU1 has full access memory region and write only memory region.

 

Read only [CPU0]/write only[CPU1] are intersected in memory map to implement inter-core communication.

 

Do you have code example to setup MMU on CPU1-3 (if is it possible) and sets different permissions to DDR3 memory access?

 

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Alex Buraga

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