Hi,
About u-boot debugging please take a look in Targeting_PA_Processors.pdf from PA\Help\PDF (chapter 5.4.6. Debugging U-Boot from NOR, NAND, SPI, and SD Card/MMC Flash Devices).
About secure debug violation, this processor BSC9132 supports a feature named "secure debug" that basically checks if the processor is in Secure Debug mode and will enable the debug flow only if the unlock key is provided. Unfortunately, please note that “Secure debug violation” is a generic error and this can means a lot of possible errors (DDR initialization failed, corrupt core, invalid JTAG/config_chain and so on) – this way because there is only one error signal/pin and the ccs can’t multiplex all types of hw errors using it.
In many cases, the secure debug violation at this board just means that you didn't configure correctly the JTAG port according with your CW/software project and not that the SoC is secured.
The QDS part has 2 JTAG ports (JTAG_COP and JTAG_EONCE), please double-check that you selected the proper one according with your project setup.
According with board manual, you can use SW8[7:8] to choose preferred option. Please take a look on this thread [1] - this is a full thread about how the JTAG Topology can be set up according with CW settings.
Regards,
Marius
[1] https://community.freescale.com/message/331538#331538
