I'm about to write a bootloader. I have found some example code (AN2295SW).
There is a function that is copied to RAM:
void FTFL_Initialization(void)
{
Word i;
// initialize pointer to ram function
ExecuteOnStack = (void(*)(void))&buffer[1];
// copy function from ROM to RAM
for(i=0;i<(128+1);i++)
buffer[i] = ((Byte*)ExecuteOnStackStart)[i-1];
// inititalization of flash clock module
FTFL_INIT_FLASH_CLOCK;
}
static void ExecuteOnStackStart(void)
{
// launch a command
FTFL_FSTAT |= FTFL_FSTAT_CCIF_MASK;
// waiting for the finishing of the command
while((FTFL_FSTAT&FTFL_FSTAT_CCIF_MASK) != FTFL_FSTAT_CCIF_MASK){};
}
Why is there a need to copy it to RAM?
Is it not safe to execute code in flash during a flash command?
What happens if an interrupt runs from flash during a flash command? Or should I disable all interrupts before any flash command like this?
__disable_irq();
// launch a command
FTFL_FSTAT |= FTFL_FSTAT_CCIF_MASK;
// waiting for the finishing of the command
while((FTFL_FSTAT&FTFL_FSTAT_CCIF_MASK) != FTFL_FSTAT_CCIF_MASK){};
__enable_irq();
Solved! Go to Solution.
Usually the flash memory are just allowed to do one thing at a time, either read or write . That is why you need to copy the function to execute the command to RAM, to avoid the "Read-While-Write" violations. Here is an app note that explains why this should be done and addresses the questions you have on ISR handling :smileyhappy:
Usually the flash memory are just allowed to do one thing at a time, either read or write . That is why you need to copy the function to execute the command to RAM, to avoid the "Read-While-Write" violations. Here is an app note that explains why this should be done and addresses the questions you have on ISR handling :smileyhappy:
The things you say are true -- you cannot let anything attempt a 'read' of a flash bank while it is writing. For two-bank parts you can just insure nothing 'runs' from the 'inactive' bank, but it is always just 'safer' to let all flash operations run from RAM. I let my whole bootloader be copied out to RAM, vector table and all, by the IAR linker setup.