I have a P2020 based system with 4GB RAM. I have been testing mSATA SSD performance which involves a x4 PCIe connection to a SATA controller. If I run the board in 2GB RAM mode I get much better performance than in 4GB RAM mode, 381 MB/sec vs. only 219 MB/sec. I noticed that in 4GB mode, I get some extra kernel log entries that appear to originate from the linux source file arch/powerpc/sysdev/fsl_pci.c, "Outbound window cfg leaves gaps in memory map...", "DMA window size is 0x8000000" (2GB). I believe the mSATA performance degradation is due to the use of SWIOTLB bounce buffers for PCI DMA when in 4GB mode.
The current Linux BSP for the board is only at kernel version 3.0.3. I came across the following downstream patch for fsl_pci.c:
Adding the code from this patch to the 3.0.3 version of fsl_pci.c significantly improved the 4GB mode mSATA performance to about 370 MB/sec, so not quite as good as when in 2GB mode.
I would like to know if it is possible to modify the memory map somehow so I end up with a 4GB PCI DMA window size instead of only 2GB. My assumption is that may provide 4GB mode performance as least as good as 2GB mode.