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Vybrid M4 core Cache Mapping

Question asked by Stefan Singer Employee on Aug 1, 2013
Latest reply on Dec 16, 2013 by jiri-b36968

Hi all, we are trying to understand, how cache mapping for the Cortex M4 core works on Vybrid. I am somewhat new to Vybrid, so the question might be simple (my personal background is mainly Power Architecture). Chapter 29 of the Vybrid RM describes the Local Memory Controller and describes static "views" of the memory, whether a certain region is non-cachable, write through, ... I can not find any setting to mark e.g. the GFX RAM non cachable. I also tried to compare the description to the Kinetis RM and there is an additional register "Cache regions mode register (LMEM_PSCRMR)", which allows to map those sections, but that register seems to be missing on Vybrid ? I have heard some comments, that the M4 core on Vybrid has an MPU and the one on Kinetis has not, so that function might be in the MPU now ? According the ARMs Cortex M documentation there should be the MPU_RASR.ATTRS fields in the MPU to define those attributes. Are those implemented on Vybrid and is there an example, how to configure this ?

 

Thanks in advance

Stefan

 

 

 

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