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Unable to clear PCIe BARs 2 and 3 on i.MX6

Question asked by ronsandel on Jul 26, 2013
Latest reply on Aug 15, 2013 by ronsandel

I am using the Boundary Devices Sabre Lite for i.MX6 with VxWorks and the BSP for that board it comes with.  It doesn't support PCIe so I am putting together my own driver.  The post I am using as guidance is: https://community.freescale.com/docs/DOC-95014

 

Basically I set all the registers and PCIe is alive and the link is good and the BAR registers show up like this:

 

0x0000000c

0x00000000

0x00000008

0x00000001

0x00000000

0x00000000

 

And when my root complex assigns memory to the them they show up like this:

 

0x8000000c

0x00000000

0x80100008

0xe8000001

0x00000000

0x00000000

 

I only need 1MB of memory in a single BAR, so similar to 0001-ENGR00268112-pcie-emaluate-the-pcie-ep-as-ram-device.patch I do this:

 

*(volatile unsigned int *)(0x01ffc000 + 0x10) = 0;

*(volatile unsigned int *)(0x01ffc000 + (1 << 12) + 0x10) = 0x100000 - 1;

 

*(volatile unsigned int *)(0x01ffc000 + 0x14) = 0;

*(volatile unsigned int *)(0x01ffc000 + (1 << 12) + 0x14) = 0;

 

*(volatile unsigned int *)(0x01ffc000 + 0x18) = 0;

*(volatile unsigned int *)(0x01ffc000 + (1 << 12) + 0x18) = 0;

 

*(volatile unsigned int *)(0x01ffc000 + 0x1c) = 0;

*(volatile unsigned int *)(0x01ffc000 + (1 << 12) + 0x1c) = 0;

 

*(volatile unsigned int *)(0x01ffc000 + 0x20) = 0;

*(volatile unsigned int *)(0x01ffc000 + (1 << 12) + 0x20) = 0;

 

*(volatile unsigned int *)(0x01ffc000 + 0x24) = 0;

*(volatile unsigned int *)(0x01ffc000 + (1 << 12) + 0x24) = 0;

 

And then the registers show up as this:

 

0x00000000

0x00000000

0x00000008

0x00000000

0x00000000

 

So it looks like my write of 0 to BAR0 and BAR3 worked but my write of 0 to BAR2 didn't.

 

And when my root complex assigns memory they show up like this:

 

0xa0100000

0x00000000

0x00000008

0xa0200000

0x00000000

0x00000000

 

So it looks like the 8 in BAR2 isn't getting cleared, although it's not a big deal because memory isn't actually being assigned to it.  But the BAR3 is still getting assigned.  I noticed a comment in the patch says:

 

/*

* 32bit prefetchable 1M bytes memory on bar3

* FIXME BAR MASK3 is not changable, the size

* is fixed to 256 bytes.

*/

 

Is that some kind of hardcoded limitation in the processor?

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