Evaluating using multiple (9x to 25x) PDM-output MEMS microphones for a digital beamformer. Instead of using multiple CODECS that process the PDM and convert to I2S or analogue, I'm using a Kinetis K70, say, processor to handle the PDM input of multiple microphones and creating an output that includes the beamforming and steering.
To generate a clock suitable for the multiple I2S ports being used, I've configured the I2S driver to output a 256x 44.1 kHz clock (tried various multiples, including 37.5 kHz x64 for exactly 2.4 MHz PDM clock requested in the ADMP521 datasheet). Then, I take the MCLK output from the I2S port and pipe it into FTM_CLKIN1 and set the Flextimer to subdivide the input clock by 4 so that I have a perfectly synchronized PDM clock of x64. Further, I use another FlexTimer to reduce down to the original for viewing the 22.5, 37.5, 44.1, or 48 kHz sample rate and observing the "density" of 1's in the PDM microphone's output.
Everything works--all the clocks are within spec and the duty cycles are very near 50% as expected, with a bit of jitter but looking tolerable.
Question: Any idea on how to bring up to N (at least 5) of these bad-boy PDM inputs into a Kinetis MCU without loading down the processor with interrupts at 3 MHz? Originally intended to use a FlexTimer as a counter, then decimate using the counter. Would like to stay digital as much as possible.
Edit: will migrate to using 4x ADuM7002 PDM to I2S (TDM) driver ICs and bring in 8x PDM microphones via I2S instead of trying to do this in software.