When operating with the MMU enabled on a V4E processor, does the vector base register contain the virtual address or the physical address of the vector table?
Reading through the MMU chapter:
126.96.36.199 Virtual Mode
Every instruction and data reference is either a virtual or physical address
mode access. All addresses for special mode (interrupt acknowledges, emulator
mode operations, etc.) accesses are physical. All addresses are physical if
the MMU is not enabled. If the MMU is present and enabled, the address mode
for normal accesses is determined by the MMUBAR, RAMBARs, and ACRs in the
priority order listed. Addresses that hit in the MMUBAR, RAMBARs, and ACRs
are treated as physical references. These addresses are not translated and
their address attributes are sourced from the highest priority mapping
register they hit. If an address hits none of these mapping registers,
it is a virtual address and is sent to the MMU. If the MMU is enabled,
the default CACR information is not used.
Is the Vector Fetch "Special" or "Normal"? Is the Vector Fetch part of the "interrupt acknowledges" or not?
The answer might be "does the address in the VBR hit in RAMBAR or the ACRs"? If it doesn't it may well get remapped.
I'd recommend putting the vectors in the SRAM if you can. That simplifies things.
I certainly wouldn't want to get a TLB Miss on the memory that contains the vector table if it is virtual! That would probably trigger an unrecoverable "Fault-on-Fault Halt".
Why not create two vector tables with different vectors for something like a PIT interrupt, remap the address of the first table to the second one and see which one supplies the vector?
Retrieving data ...