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IPU question on I.mx6

Question asked by jasonhaedt on Jul 22, 2013
Latest reply on Dec 9, 2014 by Erez Steinberg
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    Sorry to be a nuisance, but after some more digging I've got some more information on what we're seeing and I was sort hoping to do a sanity-check with you guys.  I wrote a little program to enable the profiler in the MMDC just to get a rough idea of what DDR utilization looks like in a few different scenarios.  I don't think I mentioned before, but we're running on the sabresd board right now with a little custom daughterboard to a mipi dsi display.  DDR clock is at 528MHz, and we're running around a 66MHz pixel clock.  I'm calculating utilization by just dividing MADPSR1/MADPSR0.  What I see is


    display blanked - < 1%

    display unblanked/unrotated - 28%

    display unblanked/rotated - 50%


    I was somewhat surprised by these numbers - the 28% for just the display seems a lot higher than I'd expect.  Given approximately a 66MHz pixel clock, the total bandwidth  from the memory should be around 264MByte/sec (66*4 - according to the reference manual the IPU translates everything in/out of memory to 8:8:8:8).  Peak rate for the ddr should be 528*2*64/8 = 8.4GByte/sec (and I realize peak bandwidth is a mostly useless metric here and that average throughput should be considerably lower, but it's a starting point).  Have you guys done any profiling at different resolutions/frame rates, and if so do the numbers we're seeing seem reasonable?

    Like I said, sorry to be a nuisance, but we're trying to finalize our hardware design and we're trying to get a handle on whether there are pieces of the design we need to optimize by moving certain processing operations (like screen rotation) out in to our fpga.

    Thanks again!