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Reset Core 1, 2 and 3 in iMX6

Question asked by Tiago Duarte on Jul 22, 2013
Latest reply on Jul 22, 2013 by Anson Huang

Dear all,

I'm working in a project for the University and the main goal was accomplished. The goal was to port a RTOS in bare-metal to the Nitrogen6x board, based in the iMX6 chip.

Core 0 is running the OS and my next goal was to perform tasks with the other cores (1, 2 and 3).

With this in mind I configured the SRC registers in this order (just for Core 1, for now):

     1 - Wrote the address of the function that I wanted in the register that holds entry function for CPU1 - SRC_GPR3 (The function was just a print in a while loop to verify that it was working.)

     2 - Enable the Core 1 by setting the bit 22 in the SRC_SCR.

Nothing happened.

 

After I reconfigured the startup code of the OS to support multiple cores. And my idea was to differentiate the primary core (Core 0) from the secondary cores (Core 1, 2 and 3) and jump to different functions, the primary core will jump to the main of the OS and the secondary cores will jump to my printf in a while function.

I re-configured the SRC registers in this order:

     1 - Wrote the address of the startup function in the register that holds entry function for CPU1 - SRC_GPR3.

     2 - Wrote the address of the function (the printf in a while loop) in the register that holds argument of entry function for CPU1 - SRC_GPR4. the startup code was jumping to this address after the initializations.

     3 - Enable the Core 1 by setting the bit 22 in the SRC_SCR.

 

Non of this methods worked and I could put the secondary cores working.

I have a JTAG connection to the Core 0 using openocd but unfortunately I can't connect it to the other cores because of the lack of support in the openocd documentation. I can only load and debug the Core 0 and I don't know in which state U-Boot puts the secondary cores in the cluster.

I would like to know what I'm doing wrong or if there is another process to initiate the secondary cores in a iMX6 chip.

 

Thanks in advance,

Tiago Duarte

University of Minho

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