I have a P1011 with a local bus configured to use an external LGTA (SETA=1).
I am accessing a third party FPGA with a 16-bit address bus however, the FPGA registers are 32 bit.
Each valid 32-bit read access to this FPGA produces two back-to-back LGTAs as expected - DWORD read.
An invalid 32-bit read access to this FPGA (invalid register address) produces a single LGTA. The second LGTA never gets asserted.
In my case, the bus transaction appears to have completed successfully with that single LGTA. There is no bus error indicator from the bus error monitor which is set to a 2.6 s timeout. From a SW perspective the read is unit32_t. The read appears to have completed successfully but the data is unreliable.
Under what circumstances would the P1011 be happy terminating a DWORD read with only a single LGTA?