PLL help for mc68hc908ap

[dan44137]

Hi All,

I am new to using freescale microcontrollers and would appreciate any help I can get.  I have got everything I need for my project working except the phased locked loop(PLL).  The controller seem to want to stay working at a 2Mhz bus speed.  I a clocking off a 8Mhz x-tal and want the bus frequency also at 8Mhz. Below is the register setting I have put into codewarrior. 

PCTL_PLLIE = 0;//turns off PLL interupt
  PCTL_PLLON = 0;//turn off PLL so can set P,R,N,E and L
 
  PCTL_PRE0 = 0;//sets P to 0
  PCTL_PRE1 = 0;//sets P to 0
 
  PCTL_VPR0 = 0;//sets E to 2
  PCTL_VPR1 = 1;//sets E to 2
 
  PMSH_MUL11 = 0;//sets N to 4
  PMSH_MUL10 = 0;//sets N to 4
  PMSH_MUL9 = 0;//sets N to 4
  PMSH_MUL8 = 0;//sets N to 4
  PMSL_MUL7 = 0;//sets N to 4
  PMSL_MUL6 = 0;//sets N to 4
  PMSL_MUL5 = 0;//sets N to 4
  PMSL_MUL4 = 0;//sets N to 4
  PMSL_MUL3 = 0;//sets N to 4
  PMSL_MUL2 = 1;//sets N to 4
  PMSL_MUL1 = 0;//sets N to 4
  PMSL_MUL0 = 0;//sets N to 4
 
  PMRS_VRS7 = 0;//sets L to 64
  PMRS_VRS6 = 1;//sets L to 64
  PMRS_VRS5 = 0;//sets L to 64
  PMRS_VRS4 = 0;//sets L to 64
  PMRS_VRS3 = 0;//sets L to 64
  PMRS_VRS2 = 0;//sets L to 64
  PMRS_VRS1 = 0;//sets L to 64
  PMRS_VRS0 = 0;//sets L to 64
 
  PMDS_RDS3 = 0;//sets R to 1
  PMDS_RDS2 = 0;//sets R to 1
  PMDS_RDS1 = 0;//sets R to 1
  PMDS_RDS0 = 1;//sets R to 1
  

  PCTL_PLLON = 1;//turn on PLL
  
    PCTL_BCS = 1;//set CGMPCLK to source CGMOUT
      PBWC_AUTO = 1;//Automatic bandwidth control
  while(PBWC_LOCK == 0){
  }

thanks

dan

[bigmac]

Hello Dan,

Your initialisation code might be simplified to the following.  This should also result in shorter code length.

void PLL_init(void)

{

PCTL = 0;

PCTL_PLLON = 0; // Just in case BCS was set on entry
PCTL_PRE = 0;   // Set P = 0
PCTL_VPR = 2;   // Set E = 2
PMSH = 0;
PMSL = 4;       // Set N = 4
PMRS = 64;      // Set L = 64
PMDS = 1;       // Set R = 1

PBWC = 0x80;    // Set AUTO bit for automatic BW control

                // Write all bits per Rocco's suggestion

PCTL_PLLON = 1; // Turn on PLL
PCTL_BCS = 1;   // Set CGMPCLK to source CGMOUT
while (PBWC_LOCK == 0); // Wait for lock to occur
}

Regards,

Mac

[joeservo]

bigmac, you set the clock source to the CGMVCLK before it locks.  not sure if this is a good idea.

i am having problem with the PLL locking on a design.  thought i was doing something wrong so i used processor expert to verify and here is what they came up with.  (32.768kHz crystal, 8MHz bus clk desired).

PCTL_BCS = 0;                        /* Select clock source from XTAL */
PCTL_PLLON = 0;                      /* Disable the PLL */
PMS = 977;                           /* Set the multiplier */
PMRS = 208;                          /* Set the range select */
PCTL = 0;
PCTL_VPR = 2;
PBWC = 128;                          /* Select the operating modes */
PCTL_PLLON = 1;                      /* Enable the PLL */
while(!PBWC_LOCK);                   /* Wait */
PCTL_BCS = 1;

here is my code.

PCTL_PLLON = 0;
PCTL_VPR = 1;           //E = 2 
PCTL_PRE = 0;           //P = 0            Fvrs = Lx(2^E)x125000
PMS = 0x03d1;           //N = 977             N = Fvclk/crystal  
PMRS = 0x40;            //L = 64
PMDS = 1;               //R = 1
PBWC_AUTO = 1;
PCTL_PLLON = 1;         
while (PBWC_LOCK == 0)   //wait for lock
  ;
PCTL_BCS = 1;           //switch to PLL

not sure why PE uses a value of 208 for L.  anyone have any ideas?

[rocco]

Hey Joe,

---

joeservo wrote:

not sure why PE uses a value of 208 for L.  anyone have any ideas?

---

Because they used an f(NOM) of 38.4kHz.

Notice that I had a value of 208 as well (see post #2 above). When calculating L, you use a predefined value for f(NOM), which is defined as 38.4kHz for the GP32, and is 125kHz for the AP64A. So the GP22 needs L=208 for the PLL to run at 32MHz, and the AP64A needs L=64.

The data books for both the AP64 and the AP64A call out an f(NOM) of 125kHz, even though the AP64 is designed for a 32kHz crystal, and the AP64A is designed for a 1MHz to 8MHz crystal. It would not be unprecedented for the AP64 data book to be wrong, and f(NOM) should have been 38.4MHz because it uses a 32kHz crystal (if that makes a difference to the PLL).

So the difference could be caused by:

Processor Expert generated code for the GP32 or another f(NOM)=38.4MHZ mcu, or
The AP64 data book is incorrect, but Processor Expert has it right, or
The Processor Expert people didn't notice that f(NOM) had changed in later processors.

Message Edited by rocco on 2007-08-02 04:03 PM

[ProcessorExpert]

Dear user,
what version of Processor Expert do you use? The mentioned change (f(NOM)) was already fixed in Processor Expert 2.95 and later. Try to use the latest version.
best regards
Petr Hradsky
Processor Expert Support Team
UNIS