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Setting multiple breakpoints and a program trace on MCF5216 V2 core?!

Question asked by DaveTonyCook on Jul 16, 2013
Latest reply on Jul 18, 2013 by TomE

From the description taken from the product brief shown below and the documentation provided with CodeWarrior 6.4 it should be possible to set more than 1 breakpoint. In fact I would have thought it to be a pre-requisite. However when I try to set a 2nd BP an error message tells me that I have possibly reached my hardware breakpoint limit.  Is this correct?


Also whilst the documentation (CW & Hardware REF) tell me program trace is possible I am confounded as to how one might go about it.


Any help would be greatly received. Thanks


MCF5216 Integrated Microcontroller Product Brief [Document Number: MCF5216PB Rev. 1, 08/2006]




1.2.3 Debug Module

The ColdFire processor core debug interface is provided to support system debugging in conjunction with

low-cost debug and emulator development tools. Through a standard debug interface, users can access

real-time trace and debug information. This allows the processor and system to be debugged at full speed

without the need for costly in-circuit emulators.The debug interface is a superset of the BDM interface

provided on Freescale’s 683xx family of parts.


The on-chip breakpoint resources include a total of 6 programmable registers—a set of address registers

(with two 32-bit registers), a set of data registers (with a 32-bit data register plus a 32-bit data mask

register), and one 32-bit PC register plus a 32-bit PC mask register. These registers can be accessed through

the dedicated debug serial communication channel or from the processor’s supervisor mode programming

model. The breakpoint registers can be configured to generate triggers by combining the address, data, and

PC conditions in a variety of single or dual-level definitions. The trigger event can be programmed to

generate a processor halt or initiate a debug interrupt exception.

To support program trace, the Version 2 debug module provides processor status (PST[3:0]) and debug

data (DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand

data, and branch target addresses defining processor activity at the CPU’s clock rate.