Does anyone have measured or simulated values for the above system under rather heavy CPU loading (NEON in use, cache in use)? 500 MHz CPU.
I'm executing in true microcontroller mode with no DDRX, SRAM, parallel FLASH, nothing on the external bus. I'm booting from an SPI FLASH part that loads into RAM, executes, then idles.
Peripherals in use: SAI (768Kbps), DMA (slow, 96 KB/sec)
I'm trying to design the power supplies (DC/DC or LDO) from my wall adapter input on down (wall will be 4.2V, 4.5V, or 5.0V). I could spin a board with only my exact schematic configuration plus several power options (large pcb, not final), characterize power, then spin another board with final optimal power parts -- tough on the schedule. It appears that the Tower schematic is well partitioned and I might be able to measure the current at various power header jumpers -- has anyone done this? Did measurements match the final board or were there surprises from missed rails?
Or, is there an Excel spreadsheet where I can enter various parameters for my system and see the impact on mA on the rails?