Hi, I've looked over the reference manual and have a couple of questions about the FlexBus.
The only bus timings I see appear to show that all Flexbus signals must be qualified with the FB_CLK. Please confirm, Flexbus is not an asynchronous bus.
There are diagrams of 32 bit to 8 bit port burst (looks like 6 clocks min). But, I'm interested in doing a 32 bit to 16 bit port bursts. If I do 32 to 16, how many clock cycles is the access? 4? 5?
I was really hoping to burst several 32 bit words per cycles, but I don't see that listed. I'm assumming that idea is not possible.