Exception Stack Frame MCF5216 / CodeWarrior 6.4

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Exception Stack Frame MCF5216 / CodeWarrior 6.4

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DaveTonyCook
Contributor IV

In the programmers ref man. Page 11-4 sec 11.1.2 Exception Stack Frame definition shows the stack frame format as:

 

FORMAT/ FS[3-2]/ VEC/ FS[1-0]/ STATUS REG

 

However, the boiler plate code supplied with the ARC evaluation kit for the M5282EVB development board v2.2.0 implements the exception stack frame as:

 

FS/ Fmt/ Vector/ FS/ STATUS REG

 

So my question is... which is correct? Anyone know ;0)

 

Further:

 

The macro

 

#define MCF5200_RD_SF_VECTOR(PTR)   \

      ((*((uint16 *)(PTR)) >>  2) & 0x00FF)

 

would get at bits 2 & 4 of the status register in any case, surely it should be:

 

#define MCF5200_RD_SF_VECTOR(PTR) \

( (uint16 *) ( *(PTR) >>  18) & 0x00FF) )

 

to get at bits 18 to 25 of the VEC byte??

 

The tool chain is CodeWarrior 6.4

 

Any help would be appreciated. Thanks

 

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TomE
Specialist II

> So my question is... which is correct? Anyone know ;0)

Go for a majority opinion. The Programmer's Reference Manual is correct and matches the "Coldfire Core" chapters in all the manuals.

> FS/ Fmt/ Vector/ FS/ STATUS REG

In more detail:

| Format[3:0] | FS[3:2] | Vector[7:0] | FS[1:0] | Status[15:0} |

> #define MCF5200_RD_SF_VECTOR(PTR)  \

>      ((*((uint16 *)(PTR)) >>  2) & 0x00FF)

>

> would get at bits 2 & 4 of the status register in any case, surely it should be:

Nope. Remember this is a big-endian CPU. Also, that the "Format Vector Word" is the upper 16 bits of the 32-bit word on the stack. Therefore "*((uint16 *)(PTR))" is reading "| Format[3:0] | FS[3:2] | Vector[7:0] |" and the above macro is returning "Vector[7:0] |"..

The "Vector" has two representations. First it might be the "Vector Number" (0, 1, 2, 3, 4) or it may be the "Vector Address" (0, 4, 8, 12, 16). The Macro is returning the latter.

> However, the boiler plate code supplied with the ARC evaluation

> kit for the M5282EVB development board v2.2.0 implements

>the exception stack frame as:

>

> FS/ Fmt/ Vector/ FS/ STATUS REG

I was wondering where you got that from. The "mcf5xxx.h" file that I'm using has the following in the top, which I suspect is the same as what you're looking at:

First try the Syntax Editor:

/***********************************************************************/

*

*              3322222222221111 111111

*              1098765432109876 5432109876543210

*           8 +----------------+----------------+

*             |         Program Counter         |

*           4 +----------------+----------------+

*             |FS/Fmt/Vector/FS|      SR        |

*   SP -->  0 +----------------+----------------+

*

That makes a mess of it. Try something else

Then try something else:

/***********************************************************************/ /* * The ColdFire family of processors has a simplified exception stack * frame that looks like the following: * *              3322222222221111 111111 *              1098765432109876 5432109876543210 *          8 +----------------+----------------+ *            |        Program Counter        | *          4 +----------------+----------------+ *            |FS/Fmt/Vector/FS|      SR        | *  SP -->  0 +----------------+----------------+ * * The stack self-aligns to a 4-byte boundary at an exception, with * the FS/Fmt/Vector/FS field indicating the size of the adjustment * (SP += 0,1,2,3 bytes). */ #define MCF5XXX_RD_SF_FORMAT(PTR)    \      ((*((uint16_t *)(PTR)) >> 12) & 0x00FF) #define MCF5XXX_RD_SF_VECTOR(PTR)    \      ((*((uint16_t *)(PTR)) >>  2) & 0x00FF) #define MCF5XXX_RD_SF_FS(PTR)          \      ( ((*((uint16_t *)(PTR)) & 0x0C00) >> 8) | (*((uint16_t *)(PTR)) & 0x0003) ) #define MCF5XXX_SF_SR(PTR)    *((uint16_t *)(PTR)+1) #define MCF5XXX_SF_PC(PTR)    *((uint32_t *)(PTR)+1) 

OK, that was the THIRD attempt at posting code into this totally broken editor. Now let's try Raw HTML (welcome to the 1970's) again...

/***********************************************************************/
/*
 * The ColdFire family of processors has a simplified exception stack
 * frame that looks like the following:
 *
 *              3322222222221111 111111
 *              1098765432109876 5432109876543210
 *           8 +----------------+----------------+
 *             |         Program Counter         |
 *           4 +----------------+----------------+
 *             |FS/Fmt/Vector/FS|      SR        |
 *   SP -->  0 +----------------+----------------+
 *
 * The stack self-aligns to a 4-byte boundary at an exception, with
 * the FS/Fmt/Vector/FS field indicating the size of the adjustment
 * (SP += 0,1,2,3 bytes).
 */

#define MCF5XXX_RD_SF_FORMAT(PTR)     \
     ((*((uint16_t *)(PTR)) >> 12) & 0x00FF)

#define MCF5XXX_RD_SF_VECTOR(PTR)     \
     ((*((uint16_t *)(PTR)) >>  2) & 0x00FF)

#define MCF5XXX_RD_SF_FS(PTR)          \
     ( ((*((uint16_t *)(PTR)) & 0x0C00) >> 8) | (*((uint16_t *)(PTR)) & 0x0003) )

#define MCF5XXX_SF_SR(PTR)     *((uint16_t *)(PTR)+1)
#define MCF5XXX_SF_PC(PTR)     *((uint32_t *)(PTR)+1)

The COMMENT says "FS/ Fmt/ Vector/ FS/ STATUS REG", but the CODE extracts the correct fields.

Tom

Fourth time lucky? Gee I miss Lithium. It takes me 20 minutes to do here what Lithium allowed in one click...

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TomE
Specialist II

> So my question is... which is correct? Anyone know ;0)

Go for a majority opinion. The Programmer's Reference Manual is correct and matches the "Coldfire Core" chapters in all the manuals.

> FS/ Fmt/ Vector/ FS/ STATUS REG

In more detail:

| Format[3:0] | FS[3:2] | Vector[7:0] | FS[1:0] | Status[15:0} |

> #define MCF5200_RD_SF_VECTOR(PTR)  \

>      ((*((uint16 *)(PTR)) >>  2) & 0x00FF)

>

> would get at bits 2 & 4 of the status register in any case, surely it should be:

Nope. Remember this is a big-endian CPU. Also, that the "Format Vector Word" is the upper 16 bits of the 32-bit word on the stack. Therefore "*((uint16 *)(PTR))" is reading "| Format[3:0] | FS[3:2] | Vector[7:0] |" and the above macro is returning "Vector[7:0] |"..

The "Vector" has two representations. First it might be the "Vector Number" (0, 1, 2, 3, 4) or it may be the "Vector Address" (0, 4, 8, 12, 16). The Macro is returning the latter.

> However, the boiler plate code supplied with the ARC evaluation

> kit for the M5282EVB development board v2.2.0 implements

>the exception stack frame as:

>

> FS/ Fmt/ Vector/ FS/ STATUS REG

I was wondering where you got that from. The "mcf5xxx.h" file that I'm using has the following in the top, which I suspect is the same as what you're looking at:

First try the Syntax Editor:

/***********************************************************************/

*

*              3322222222221111 111111

*              1098765432109876 5432109876543210

*           8 +----------------+----------------+

*             |         Program Counter         |

*           4 +----------------+----------------+

*             |FS/Fmt/Vector/FS|      SR        |

*   SP -->  0 +----------------+----------------+

*

That makes a mess of it. Try something else

Then try something else:

/***********************************************************************/ /* * The ColdFire family of processors has a simplified exception stack * frame that looks like the following: * *              3322222222221111 111111 *              1098765432109876 5432109876543210 *          8 +----------------+----------------+ *            |        Program Counter        | *          4 +----------------+----------------+ *            |FS/Fmt/Vector/FS|      SR        | *  SP -->  0 +----------------+----------------+ * * The stack self-aligns to a 4-byte boundary at an exception, with * the FS/Fmt/Vector/FS field indicating the size of the adjustment * (SP += 0,1,2,3 bytes). */ #define MCF5XXX_RD_SF_FORMAT(PTR)    \      ((*((uint16_t *)(PTR)) >> 12) & 0x00FF) #define MCF5XXX_RD_SF_VECTOR(PTR)    \      ((*((uint16_t *)(PTR)) >>  2) & 0x00FF) #define MCF5XXX_RD_SF_FS(PTR)          \      ( ((*((uint16_t *)(PTR)) & 0x0C00) >> 8) | (*((uint16_t *)(PTR)) & 0x0003) ) #define MCF5XXX_SF_SR(PTR)    *((uint16_t *)(PTR)+1) #define MCF5XXX_SF_PC(PTR)    *((uint32_t *)(PTR)+1) 

OK, that was the THIRD attempt at posting code into this totally broken editor. Now let's try Raw HTML (welcome to the 1970's) again...

/***********************************************************************/
/*
 * The ColdFire family of processors has a simplified exception stack
 * frame that looks like the following:
 *
 *              3322222222221111 111111
 *              1098765432109876 5432109876543210
 *           8 +----------------+----------------+
 *             |         Program Counter         |
 *           4 +----------------+----------------+
 *             |FS/Fmt/Vector/FS|      SR        |
 *   SP -->  0 +----------------+----------------+
 *
 * The stack self-aligns to a 4-byte boundary at an exception, with
 * the FS/Fmt/Vector/FS field indicating the size of the adjustment
 * (SP += 0,1,2,3 bytes).
 */

#define MCF5XXX_RD_SF_FORMAT(PTR)     \
     ((*((uint16_t *)(PTR)) >> 12) & 0x00FF)

#define MCF5XXX_RD_SF_VECTOR(PTR)     \
     ((*((uint16_t *)(PTR)) >>  2) & 0x00FF)

#define MCF5XXX_RD_SF_FS(PTR)          \
     ( ((*((uint16_t *)(PTR)) & 0x0C00) >> 8) | (*((uint16_t *)(PTR)) & 0x0003) )

#define MCF5XXX_SF_SR(PTR)     *((uint16_t *)(PTR)+1)
#define MCF5XXX_SF_PC(PTR)     *((uint32_t *)(PTR)+1)

The COMMENT says "FS/ Fmt/ Vector/ FS/ STATUS REG", but the CODE extracts the correct fields.

Tom

Fourth time lucky? Gee I miss Lithium. It takes me 20 minutes to do here what Lithium allowed in one click...

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