"Simple SCI" doesnt work on S12xDP512

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"Simple SCI" doesnt work on S12xDP512

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underwood
Contributor I

Hello,

 

I'm triying to run the example Code on my MC9S12xDP512 CPU with XGATE enabled. (AN3144SW)

Unfortunately it doesnt work.

 

1) The Code is written for MC9S12xDT512     -     I dont know if this makes trouble

2) In the main.c the tBuffer struct (Buffer0) which is defined as "extern tBuffer Buffer0 ;" never gets filled with values. So the struct is empty the whole time and nothing will be send!!

 

3) When Running in Simulation Mode Simple SCI only works when I switch the two declarations of tBuffer Buffer0. That means in main.c there has to be  "tBuffer Buffer0;" and in the xgate.cxgate there's "extern tBuffer Buffer0;" But when I try to run this on my microcontroller the prograsmm stops after a few milliseconds with: "Exeption: Interrupt (Vector 20)"

 

Can someone help me?

 


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Monica
Senior Contributor III

Hello Lino!

We'd like to know how is the project going?

You found those examples useful? Please let us know :smileywink:

Regards,

Monica.

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underwood
Contributor I

Thanks for your help!

I just entered the SCIx handlers in both interrupt vector tables (xgate and s12x) and it worked. I just didn't want the _sif() called by SCI in xgate_vectors.cxgate to jump back to main, which even didn't work!!!!!!!!. Now it jumps to S12x_vectors.c where it belongs in my opinion!!

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RadekS
NXP Employee
NXP Employee

I would like to apologize for our delay.

You are right, there is issue in AN3144SW. I will report this issue to our documentation team.

About 1)

No, in this case – difference between XDT and XDP is just in size of RAM, number of CANs and one IIC module – nothing important.

About 2)

Since Buffer0 is used by both cores, it must be placed in RAM area which is visible by both cores. Please add placement definition for Buffer0 definition – For example:

@main.c

#pragma DATA_SEG SHARED_DATA

extern tBuffer Buffer0;

#pragma DATA_SEG DEFAULT

@xgate.cxgate

#pragma DATA_SEG SHARED_DATA

tBuffer Buffer0;

#pragma DATA_SEG DEFAULT

SCI baud rate setting is adjusted for 25MHz bus clock however example code doesn’t contain PLL initialization. Please update SCI baud rate settings according your bus clock and requested speed.

For example: I used 16MHz crystal therefore bus clock = 8MHz. SCI0BD = bus clock/16/baud rate=8000000/16/19200=26

AN3144SW initialize also terminal window however this terminal has to be set according your demands, or you can close Terminal window and use any other terminal like Hyper terminal inside WinXp.

Please go to menu-Terminal-Configure connections-Select Defaul Configuration (for example Serial port)-Set appropriate serial port and BaudRate.

About3)

Unfortunately simulation of interrupts isn’t very convenient. If it is possible I would like to recommend testing code on real device.

Note: In attachment you can find another simple example code for “SCI gateway”.

I hope it helps you.