How does the flash line buffer(cache) work in MPC5604B work when data is accessed from flash? Does it cause Flash line buffer update, in turn incurring wait states for the next instruction?
If yes, is there a work around for this?
Key elements of the flash module include the flash array and its line buffers. Line buffers allow overlapping fast access between the crossbar and a flash module line buffer with a slower access between a line buffer and the flash array.
The internal flash supports 32 bit accesses. The flash access performance is depending on the configuration of the flash and the system frequency. The best performance is reached when the prefetch buffers are enabled and there is a buffer hit. In this case 2 cycles are required to read data from the flash (1 address cycle and 1 data cycle).
The worst case access time is when the requested data is not located in the buffer (buffer miss) and the data has to be read directly from the flash. In this case additional waits states can be added. RWSC in the Platform Flash Configuration Register 1 controls the wait states depending on the system frequency (please see RM). It is also possible to add more waits states using the wait-state emulation feature. If a flash area is mapped in the memory area between 0x01000000 – 0x1FFFFFFF then depending on the address additional waits states can be added (0 to 31 wait states).
I am looking for the answer how does flash line buffer work on MPC5644A, I came through this forum, and your answer helps to clarify my problem. But I still have a couple questions.
How about the field APC in the Platform Flash Configuration Register ? When a buffer miss occur, does we need to add an additional wait state for the address pipeline? To be more precise, when do the flash need to do the address pipeline? How does it work?
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