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Can anyone please give me a simple spi without interrupt drivers for mkl25z128vlk4 i m trying to interface a DAC IC MCP4912 with mkl25z128vlk4 but i m not getting required output pls check the below code  and help me????

Question asked by Akshay H V on Jul 8, 2013
Latest reply on Jul 10, 2013 by Akshay H V

#include <MKL26Z4.H>

#include "mem.h"

#include "common.h"

#define DACA       0           // VoutA

#define DACB       1           // VoutB

#define _USING_SSP               SPI1

//#define baudrate                  0x02

#define MASTER   0x10

 

 

 

 

void spi_init( void )

{

  SIM_SCGC4 =SIM_SCGC4_SPI1_MASK;   //Enable SPI0 Clock gate

  //SIM_COPC &= (~SIM_COPC_COPT_MASK); //Disable COP Watchdog

  SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK|SIM_SCGC5_PORTB_MASK|SIM_SCGC5_PORTD_MASK|SIM_SCGC5_PORTE_MASK|SIM_SCGC5_PORTC_MASK; 

    // disable SPI

  SPI1_C1 &= ~SPI_C1_SPE_MASK;       

       /* PORTE_PCR4 &= ~PORT_PCR_MUX_MASK;                   //spi1_cs

  PORTE_PCR4 |= PORT_PCR_MUX(2)|PORT_PCR_DSE_MASK;  //Use PTE4 as SPI1_SS_b

        PORTE_PCR1 &= ~PORT_PCR_MUX_MASK;                        //sin

  PORTE_PCR1 |= PORT_PCR_MUX(2)|PORT_PCR_DSE_MASK;  //Use PTE1 as SPI1_MISO

      PORTE_PCR3 &= ~PORT_PCR_MUX_MASK;                        //dout

// PORTE_PCR3 |= PORT_PCR_MUX(2)|PORT_PCR_DSE_MASK;  //Use PTE3 as SPI1_MOSI

  PORTE_PCR3 |= PORT_PCR_MUX(3)|PORT_PCR_DSE_MASK;  //Use PTE3 as SPI1_MOSI

        PORTE_PCR2 &= ~PORT_PCR_MUX_MASK;                   //spi1_sck

  PORTE_PCR2 = PORT_PCR_MUX(2)|PORT_PCR_DSE_MASK;  //Use PTE2 as SPI1_SCK*/

// PORTE_PCR4 &= ~PORT_PCR_MUX_MASK;                   //spi1_cs

// PORTE_PCR4 |= PORT_PCR_MUX(2)|PORT_PCR_DSE_MASK;  //Use PTE4 as SPI1_SS_b

//         PORTE_PCR1 &= ~PORT_PCR_MUX_MASK;                        //sin

// PORTE_PCR1 |= PORT_PCR_MUX(2)|PORT_PCR_DSE_MASK;  //Use PTE1 as SPI1_MISO

 

 

              SPI1_C1|=MASTER;

 

        PORTE_PCR3 &= ~PORT_PCR_MUX_MASK;                        //dout

  PORTE_PCR3 |= PORT_PCR_MUX(3)|PORT_PCR_DSE_MASK;  //Use PTE3 as SPI1_MOSI

        PORTE_PCR2 &= ~PORT_PCR_MUX_MASK;                   //spi1_sck

  PORTE_PCR2 = PORT_PCR_MUX(2)|PORT_PCR_DSE_MASK;  //Use PTE2 as SPI1_SCK

 

 

 

 

 

 

  //SPI0_C1 |= SPI_C1_MSTR_MASK;  //-----master----bus clock is 12.5Mhz--0.08us--

  //SPI0_BR = 0x02;

              //  SPI0_C1 &= (~SPI_C1_MSTR_MASK);

  //SPI0_BR = 0x43;  //SPPR = 4, SPR = 3, bps div = (SPPR+1)*2^(SPR+1) = 80,----Tspi--6.4us

  //SPI0_BR = 0x40; //bps div = 10,---------0.8us

  //SPI0_BR = 0x30; //bps div = 8,----------0.64us

  //SPI0_BR = 0x10; //bps div = 4,----------0.32us

  //SPI0_BR = 0x00; //bps div = 2,----------0.16us----6.125Mhz

  //SPI0_BR = 0x54; //bps div = 192,----------15.36us

  //SPI0_BR = 0x77; //bps div = 2048,----------163.84us

               // SPI0_BR = 0x00;

// SPI0_C1 |= SPI_C1_SSOE_MASK;      //|SPI0_C1_CPOL_MASK|SPI0_C1_LSBFE_MASK;

// SPI0_C2 |= SPI_C2_MODFEN_MASK;

 

 

// SPI0_C1 |= SPI_C1_CPHA_MASK;

// SPI0_C1 &= (~SPI_C1_CPHA_MASK);

// SPI0_C1 |= SPI_C1_CPOL_MASK;

// SPI0_C1 &= (~SPI_C1_CPOL_MASK);

// //SPI0_C1 |= SPI_C1_LSBFE_MASK;

// SPI0_C1 &= (~SPI_C1_LSBFE_MASK);

 

 

  //SPI0_C1 &= (~SPI0_C1_SPIE_MASK);     //Disable RX interrrupt

  //SPI0_C1 |= SPI0_C1_SPIE_MASK;       //enable RX interrrupt 

  //SPI0_C1 &= (~SPI0_C1_SPTIE_MASK);   //Disable the transmit interrupt

  //SPI0_C1 |= SPI0_C1_SPTIE_MASK;     //Enable the transime interrupt

               

// SPI1_C1 |= SPI_C1_MSTR_MASK;

// SPI1_BR = 0x02;

//   SPI1_C1 |= SPI_C1_MSTR_MASK;

     

 

  SPI1_BR = 0x02;

    // SPI1_C1 &= (~SPI_C1_MSTR_MASK);  //---slave----bus clock is 12.5Mhz--0.08us--

  //SPI0_BR = 0x43;  //SPPR = 4, SPR = 3, bps div = (SPPR+1)*2^(SPR+1) = 80,----Tspi--6.4us

  //SPI0_BR = 0x40; //bps div = 10,---------0.8us

  //SPI0_BR = 0x30; //bps div = 8,----------0.64us

  //SPI0_BR = 0x10; //bps div = 4,----------0.32us

  //SPI0_BR = 0x00; //bps div = 2,----------0.16us----6.125Mhz

  //SPI0_BR = 0x54; //bps div = 192,----------15.36us

  //SPI0_BR = 0x77; //bps div = 2048,----------163.84us

               // SPI1_BR = 0x01;

// SPI1_C1 |= SPI_C1_SSOE_MASK;     

//   SPI1_C2 |= SPI_C2_MODFEN_MASK;

  SPI1_C1 &= (~SPI_C1_CPHA_MASK);

  SPI1_C1 |= SPI_C1_CPHA_MASK;

  SPI1_C1 &= (~SPI_C1_CPOL_MASK);

  SPI1_C1 |= SPI_C1_CPOL_MASK;

 

  SPI1_C1 |= SPI_C1_LSBFE_MASK;

  SPI1_C1 &= (~SPI_C1_LSBFE_MASK);

 

 

               

  //SPI1_C2 |= SPI_C2_RXDMAE_MASK;

  //SPI0_C2 |= SPI_C2_TXDMAE_MASK;

  //SPI0_C2 |= SPI_C2_RXDMAE_MASK;

  //SPI1_C2 |= SPI_C2_TXDMAE_MASK;

 

  //SPI0_C1 |= SPI_C1_SPE_MASK;

  SPI1_C1 |= SPI_C1_SPE_MASK;

 

}

void Delay_6us1(void)

{

  volatile uint32_t i;

for (i = 120; i > 0; i--);

}

 

 

void spi_send(uint8_t var)

{

//while(!(SPI1->S & SPI_S_TXFULLF_MASK));

// {

// }

// val->DL=var;

  //val->DH=var;

  //SPI1->DH=var;

  while ((SPI_S_REG(SPI1_BASE_PTR) & SPI_S_SPTEF_MASK) == 0x00); // wait for TX to become empty

 

 

  SPI_D_REG(SPI1_BASE_PTR) = var;

}

void DAC_convert_long(char outputSelect, int data)

{

     uint8_t upper;

    uint8_t lower;

 

 

     if (outputSelect == DACA)

     {

        upper = 0x70;//0b01110000;   //DACA,buffered,outpugain selection is 5v(GA=1) i.e Vout=1x(Vref*D/1023)

     }

     else

     {

        upper = 0x02;//0b11110000;  //DACB,buffered(BUF=1),Output gain selection 5v

     }

     upper = upper | ((int)(data >> 6));

     lower = (int)(data << 2);

  //SHDN=1;

  

  FPTB->PCOR = 1<<1;

  FPTB->PSOR = 1<<0;

 

 

  spi_send(/*_USING_SSP*/upper);

  spi_send(/*_USING_SSP*/lower);

 

 

  Delay_6us1();

  Delay_6us1();

  Delay_6us1();

  Delay_6us1();

 

  FPTB->PCOR = 1<<0;

  FPTB->PSOR = 1<<1;

 

 

 

 

}

void cs_ldac_init(void)

{

  SIM->SCGC5    |= (1 << 10) | (1  <<  12);

  PORTB->PCR[0] = (1 <<  8);                      /* ptb0 Pin for Ldac */

  PORTB->PCR[1] = (1 <<  8);                      /* ptb1 Pin for CS */

  FPTB->PDDR =( 1 << 0 | 1 << 1);

}

 

 

int main(void)

{

  cs_ldac_init();

  spi_init();

  while(1)

  {

  DAC_convert_long(DACA, 00);

  DAC_convert_long(DACA, 100);

  DAC_convert_long(DACA, 200);

  DAC_convert_long(DACA, 300);

  DAC_convert_long(DACA, 400);

  DAC_convert_long(DACA, 500);

  DAC_convert_long(DACA, 600);

  DAC_convert_long(DACA, 700);

  DAC_convert_long(DACA, 800);

  DAC_convert_long(DACA, 900);

  DAC_convert_long(DACA, 1023);

 

 

  DAC_convert_long(DACB, 00);

  DAC_convert_long(DACB, 100);

  DAC_convert_long(DACB, 200);

  DAC_convert_long(DACB, 300);

  DAC_convert_long(DACB, 400);

  DAC_convert_long(DACB, 500);

  DAC_convert_long(DACB, 600);

  DAC_convert_long(DACB, 700);

  DAC_convert_long(DACB, 800);

  DAC_convert_long(DACB, 900);

  DAC_convert_long(DACB, 1023);

  }

}

 

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