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Using a GPIO for triggering and halting the eDMA on the kinetis K70 platform.

Question asked by Claus Stovgaard on Jul 8, 2013
Latest reply on Jul 9, 2013 by Claus Stovgaard

Hi folks.


I have a setup where a FPGA is connected to a K70 MCU over the FlexBus. After some work writing and reading registers of the FPGA works quite well. Now I though have a problem, which I do not know how to solve.

I would like to use the eDMA of the Kinites to empty a FIFO on the FPGA. I have a pin from the FPGA connected to a GPIO of the MCU, indicating when there is 16 byte or more in the FIFO.  (It fits with the burst size of the eDMA). The data generated on the FPGA, is larger than what can be buffered in the FIFO, so I need to empty the FIFO while it is generated. I know how much data is generated, though not how fast it is generated, so the FPGA need to be able to halt the eDMA to prevent it reading garbage from a empty buffer.


So how to I set the DMA up to starting transferring when a GPIO change level up, and halting when changing level to down?


I have looked into the registers of the channel, but have not seen something, which can help me solve this problem.


Any ideas for how to easy empty a FIFO where I do not know how much data is available, but only how much data there is in the end is more than welcome.


Thanks ahead