I have a problem with MPC5566.
When I'm trying to invalidate the L1 cache memory using CFI bit in L1CSR0 register, it always fails (Rise of CABT bit) when an external interrupt is pending.
(Even when the cache is empty).
If I acknowledge the interrupt by reading IACKR register (and clearing the external IT pending bit in EISR register), the cache invalidation works fine again.
It is quite annoying as my cache invalidation can be in a decrementer interrupt that has to be processed before the external IRQ.
Can someone confirm that cache invalidation is impossible in this specific case ? Have you a workaround ?