I'm having trouble with the internal LDO of the i.MX53. I have a custom design and some boards do not power up correct. When switching on these modules the LDO voltages provided via VDD_ANA_PLL and VDD_DIG_PLL do not reach their voltage level (1.3V and 1.8V), but ramp up very slowly to a kind of lower and undefined voltage level. In some rare cases also these boards power up fine and the LDO voltages are as expected (1 out of 10 times).
I cheked that no IO pins are externally driven while the IO power supply for the pin (NVCC_xxx) is off and power sequencing should be fine.
To analyze the problem I modified my board to provide only 1V3 for NVCC_SRTC_POW and VCC. After 1V3 supply is stable I supply 2V5 for VDD_REG. At this time I would expect VDD_DIG_PLL and VDD_ANA_PLL to provide 1V8 and 1V3.
Regarding VDD_REG this is the only requirement for the power up sequence: "VDD_REG supply is required to be powered ON to enable DDR operation. It must be powered on after VCC and before NVCC_EMI_DRAM."
Any explanation? Are there any other requirements for the LDOs to turn on right?