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iMX6 SPI SS difference

Question asked by Clive Rolston on Jun 26, 2013
Latest reply on Jul 3, 2013 by Robin Gong
Branched to a new discussion


We have 2 ECSPI interfaces configured on our iMX6 quad core SPI2 and SPI3. We want to read  96 bytes in on the MISO line. This works fine on SPI2 - the SS stays low for the duration of the read. On SPI3 SS goes high between each byte. Our SPI drivers are identical, as far as we can tell. Is there any difference between the SPI interfaces on the chip?

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