My application is going to use VLLS0 and wake up on a falling edge on PTD4/LLWU_P14.
Should I set all other GPIO to input mode before going to VLLS0?
AN4503 says the following:
Reduce pin loading of the MCU. When the MCU sources current through the output pins, the power is being
sourced through MCU_VDD. This is most evident when you output high frequency signals to an output pin as
you might with the FlexBus clock and address/data pins.