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DDR3 clock connectivity on iMX6

Question asked by Mark Siggins on Jun 20, 2013
Latest reply on May 20, 2016 by Yuri Muhin

Hi all.

 

I've just noticed that on the iMX6 dev boards, both clocks for the DDR3 memories, are connected to the dram chips. i.e. sdclk0 and sdclk1 signals, even though in the 64-bit configurations used, all four rams are in CS0 space. Is this an error? If so, why does it still work? I would imagine that the calibration features rely on these connections being correct.

 

If, on our own board, a Solo design, so only 32-bit bus, with four 128Mx16 parts, I connect the clocks to the right rams, will it work?

 

i.e. two rams on CS0, one for d0-d15, the other for d16-d31. These driven by sdclk0 pair, sdcke0, etc.

The other two rams on CS1, one for d0-d15, the other for d16-d31. These driven by sdclk1 pair, sdcke1, etc.

 

This would make sense, right? So, why do the eval boards connect sdclk1 signals, to anything?

 

 

Many thanks,

 

Mark.

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