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i.mx6 Aptina AR0330 MIPI driver

Question asked by Ivan Kozic on Jun 17, 2013
Latest reply on May 17, 2017 by STone Alexander
Branched to a new discussion

Hi all,


I am having major difficulties in making AR0330 run on an i.mx6 system. I am fairly new to i.mx6 / Linux, but I'm getting into it quite fast - Nevertheless, I was wondering if someone could give me some pointers on how to proceed, as currently I am stuck.


I have written a driver for Aptina AR0330 based on OV5640 MIPI driver. The concept is the same, although Omnivision has some different commands and settings. Virtual channel should be fixed to 0 by Aptina, whereas with Omnivision it is selectable through a register. MIPI is functional, but after that something goes wrong.


Currently, I believe that the major issue is the format - OV has YUV, while Aptina has Bayer pattern. The RM for i.mx6Q specifies that on-the-fly processing on the IPU for Bayer pattern is not supported (I don't really know what this means - I guess it has to buffer a frame to the memory first).

I have set up 2 lanes and MIPI is working I suppose (no ERR regs). Mipi format is set to RAW12 (as sensor outputs 12 bits). V4L puzzles me - there is a ioctl in the driver which is used to set the V4L format (ioctl_g_ifparm) with the following code:


     p->u.bt656.clock_curr = ar0330_data.mclk;

     p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;

     p->u.bt656.clock_min = AR0330_XCLK_MIN;

     p->u.bt656.clock_max = AR0330_XCLK_MAX;

     p->u.bt656.bt_sync_correct = 1;  /* Indicate external vsync */


I am not really sure why the clock is used here (I have just copied OV settings) - AR0330 uses fixed clock that comes from crystal (24MHz)?

Also not sure why BT656 is used in the whole story?


Also, OV5640 is connected to CSI1 of IPU0, using the Virtual channel 0. In RM, in the CSI2IPU gasket it is specified that VC0 is connected to CSI0 of IPU0, so I'm not really sure what is going on there as well, as people seem to be using this driver "as-is" and it works?


So in general, I have an issue understanding V4L2 - as far as I could see from DS and RM the pipeline is something like:




I am guessing V4L is used to init this whole pipeline (IPU mainly, as MIPI is initialized by the driver) and fetch data from this memory. Please correct me if I'm wrong.

So, I would be very grateful if someone could answer my questions and point me in the right direction if I'm wrong somewhere...

Thanks in advance!