I am working on i.MX6 platform, I found the use of fractional part of DI Base Sync Clock Gen 0 Register (IPUx_DIx_BS_CLKGEN0)
is not always a good idea. I am using external PLL clock to drive clk_di_pixel clock to generate proper clock rate for HDMI display,
but when use fractional part of CLKGEN0, clock will be unstable and the PLL is not working properly, or rather doesn't work at all.
This makes me believe there probably is a chip bug with fractional part of DI Base Sync Clock Gen 0 register.
Bug I can't find any information about this in i.MX6 user reference manual,
Could anyone in Freescale help me to clarify on this?