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imx6 CSI and TW9960

Question asked by Thorsten Schmelzer on Jun 13, 2013
Latest reply on Aug 8, 2013 by Thorsten Schmelzer
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Hi community,


I am trying to use the composite video decoder chip TW9960 on the parallel CSI of the i.MX6 (Dual). We only have the data pins and the pixelclock connected so I want to use BT656 internal SAV and EAV signals. I have created a driver based on the one for the adv7180. Basically the driver is working. I2C communication to the TW9960 is working, the corresponding slave ioctrls are called inside my driver form the mxc_v4l2_capture driver. I have set the following parameters in my ioctl_g_ifparm:


parm->if_type = V4L2_IF_TYPE_BT656; /* This is the only possibility. */

parm->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_BT_8BIT;

parm->u.bt656.bt_sync_correct = 1; // also tried with =0 does not seem to make a difference

parm->u.bt656.clock_curr = 0;

parm->u.bt656.latch_clk_inv = 1;


As test applications I use the ones from the imx-test package (mxc_v4l2_still.out, mxc_v4l2_capture.out and mxc_v4l2_tvin.out). Everything seems to work until I get to the point where the data is actually captured. For for the mxc_v4l2_still I get an:

ERROR: v4l2 capture: mxc_v4l_read timeout counter 0


When using mxc_v4l2_capture.out or mxc_v4l2_tvin.out I get an:

ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0


Both errors seem to indicate that we are waiting for an EOF interrupt which does not occur. We measured the output stream of the TW9960 and it seem to produce a valid bt656 video signal. It is also generating the EAV and SAV fields inside the stream. This led me to the CSI configuration in ipu_csi_init_interface, file ipu_capture.c. For clock mode IPU_CSI_CLK_MODE_CCIR656_INTERLACED the registers CSI_CCIR_CODE_1/2/3 are written depending on wether PAL or NTSC is used (the camera we are using on the tw9960 is a PAL camera). The meaning of CSI_CCIR_CODE_3 register is quite clear to me. But the description of CSI_CCIR_CODE_1/2 sound rather unspecific. I assumed that the 3-bit fields are representing the F,V and H bits in EAV and SAV codes in the bt656 stream. And theses registers have to be set accordingly to the data produced by the video input stream. However the datasheet does not specify the order (or usage) of the individual bits. Can anyone confirm my assumtion?


Any other suggestions what I could check?


I am enabling parallel video inputs in my board configuration file with:

/* enable parallel input for IPU1 CSI0 */

mxc_iomux_set_gpr_register(1, 19, 1, 1);

/* enable parallel input for IPU2 CSI1 */

mxc_iomux_set_gpr_register(1, 20, 1, 1);


Thanks and regards

Thorsten Schmelzer