Would like to enable the data cache at startup assembly file. Can anyone guide me how to access the control registers and what are the steps I need to follow?
Thanks in advance for your time and help!
Taking a look in the RM for e200 core  , this should be something like:
Note that 1010 is an index for L1CSR0 core register and 1013 is an index for BUCSR core register.
Thanks for the info!
In my task I have to specify a portion of SRAM for Data as DATA CACHE using MMU TLB table. I am not sure how MMU works with PPC. If any help to configure the memory as a data cacheable would be appreciated. Something like how to assign the RAM memory and command the controller that is use as Internal data cache.
Please find below an example about how can configure cacheable a TLB entry:
For SRAM initialization you can take a look in the processor Reference Manual.
Thank you very much! This helps me.
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