MFC5272 clock change

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MFC5272 clock change

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louis_springbok
Contributor I

I've have a board that used to run everything off a 48MHz clock. We have a new board revision that attempts to switch this with a 62.5MHz clock (48MHz is still available for USB clock) and we aren't able to program it anymore.

 

I'm attempting to program it using PE Micro's "PROGCFZ Programmer" and a ColdFire BDM connector and we get the error "35 - Not able to access processor. Try a software reset." If we jumper back to the 48MHz clock everything programs fine.

 

The 5272 can run up to 66MHz so I would assume 62.5MHz is a valid operating frequency.

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Monica
Senior Contributor III

Hello Louis,

have you been able to check Tom's suggestions? Please keep us posted, we'd like to know! :smileywink:

Best regards,

Monica.

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louis_springbok
Contributor I

I did look into his suggestions. The clock had several issues with it in that is was been used to drive several chips across the PCB. After getting proper termination of the clock run I was able to meet the specs for rise/fall time and duty cycle. After this and trying different wait states with the programmer we were still not able to program it with the 62.5MHz clock.

This is a time sensitive project so we decided to stick with the 48MHz clock as there were no issues with this and we need this to be reliable.

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TomE
Specialist II

Have you check the PE Micro forums? I couldn't find anything matching in a quick search, but taking longer may be worthwhile. PE also answers questions posted to the forum.

Here's one related to changing clock frequencies - I don't know if it applies to your chip:

http://www.pemicro.com/forums/lofiversion/index.php?t2798.html

Tom

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TomE
Specialist II

Could it be this:

23.3.3 Processor Bus Output Timing Specifications

NOTE

Above 48 MHz, the memory bus may need to be configured for one wait

state. It is the responsibility of the user to determine the actual frequency at

which to insert a wait state since this depends on the access time of SRAM

or SDRAM used in a particular system implementation.

The Debugger might be trying to access external memory and may need to be changed to add the wait states when it first programs the CPU.


You may need to reprogram the SDRAM controller for the higher speed.


You should also check to see if there are any known issues with the debugger when you speed the CPU up - with the Debugger manufacturer.


Also check the Duty Cycle of the new clock you're generating. It must be better than 45/55% to meet the CPU specs. Also the rise time:


23.3.1 Clock Input and Output Timing Specifications


If you program a CPU at 48MHz and then restrap it to 62.5MHz does it run? This might help to isolate the problem as being with the CPU or with the debugger.


Tom


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