Hello, i want use 32bit bus DDR3.
In references with 64bits bus, used DRAM_SDCLK1 diff. signal.
In 32bit also may use DRAM_SDCLK1 or need use DRAM_SDCLK0?
Pavel, good day !
really we can consider the DRAM_CLK0 and DRAM_CLK1 as the same clock.
But jitter should be taken into account, even when we use the same clock source,split via buffers.
You can refer to DDR3 connections on i.MX53_Tablet_Design for your 32bit DDR3 bus. Please see attachment.
I'm dont understand ... why imx53 schematic ...
schematic of imx53 not have questions, because bus is 32bits
imx6 have 64bits and i can't find references schematic with 32bit and datasheet don't have any instruction about CLK0/1 selection.
I have ever confirmed the similar question with HW dept, it is no problem to use low 32bit bus of i.mx6 memory interface.
In i.MX SoC , The clock source of CLK0 & CLK1 is the same. So you can use them like this:
(1) Using same clock for reading or writing one 32 bit .
CS0: D0~D31 ( 2 DDR3 ICs)
CS1: D0~D31 (2 DDR3 ICs)
CLK1(2) Every 16bit uses same clock.
CS0: D0~D15 (1 DDR3 IC)
CS0: D16~D31 (1 DDR3 IC)
CS1: D0~D15 (1 DDR3 IC)
CS1: D16~D31 (1 DDR3 IC)
The above mothod is for you as a reference.
This variant is already possible?
if you do like this, Is it convenient to control diffrential resistance of CLK1 during PCB design ?
In order to control resistance conveniently, I recommend 2nd solution:
(2) Every 16bit uses same clock.
It simply question, i get 3 reply without simply answer
I don't need recommendations and comments, please just tell me DRAM_CLK0 and DRAM_CLK1 it is fully equal or have specific with CS0/1
About recommendations, see pinout imx6, CLK0 and CLK1 is morror placed, as result - in references D0-D31 connected to CLK1 and D32-D63 connected to CLK0
Please refer to Yuri's advice for you ! I agree with him, too .
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