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P4080 PCIe Flash vbank clarification

Question asked by Stanislav Perepelitsa on May 27, 2013
Latest reply on May 27, 2013 by Marius Grigoras

My problem comes from absence of detailed hardware specification for P4080 PCIe board, also known as Niagara 710.

So I can only guess how did they implement Flash virtual bank switching.

From brief hardware specification I know that there is 1Gb NOR Flash on board.

In documentation it is suggested to put all experimental images to  vBank4

 

So, being booted from vBank0 we see:

0xEBF8_0000    <- address to place uBoot image (vBank4)

......

0xEBFF_FFFc    <-  address to start execution from (vBank4)

---------------------------------

0xEC00_0000     <-   address to place RCW. (vBank4)

 

Then  $>n710_reset altbank do some magic and the following translation should happen

Address:

0xEC00_0000 should translate to 0x0000_0000

0xEBF8_0000 -//- to 0xFFF8_0000

 

Basically we need to translate 0xEC to 0x00 and 0xEB to 0xFF, but can't imagine a simple circuit to perform such translation.

My another problem is about uBoot image size. It should be constant to keep recommended placement address valid.

Else we have a real chance to miss expected boot vector location.

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