The Vybrid series uses a LDO (external NPN) to create 1.2V from the 3.3V. I already have a switcher on the PCB which generates 1.2V so my question is, can I use that 1.2V line to power the core directly?
Thanks and best regards,
Let me first answer the simpler question “Can I bring an externally generated 1.2V to the VDD12_AFE pin?” – No, you cannot power the 1.2V digital (core) portion of the IC and the analog 1.2V (AFE) one from 2 different sources; based on the ‘Power-Up Sequencing’ table in the Datasheet , they both have to turn on/off simultaneously (the easiest way of doing that is using the same 1.2V source but filtered for the analog power rail).
Regarding the second question: it is indeed very appealing to use a 1.2V source existing in your design, external to the Vybrid IC, which, by the way, is also much more efficient and generates less heat than the existing NPN-based one (called HPREG in the Datasheet).
This approach can be used, but, unfortunately, it is impossible to simply get rid of the NPN transistor and connect the on-board 1.2V source to the IC core power balls (and the BCTRL output is not digital but analog belonging to the built-in linear voltage controller to supply 1.2V to the IC core).
The reason for that is that the IC switches between various modes, High and Low-Power ones, so that only internal blocks and the BCTRL output are controlled (with quite strict timing), without any digital signals going out to control any external voltage supply.
At the same time, we are already working in this direction – running simulations (results are good) and preparing hardware for testing. Although our new scheme is quite straightforward, the customers are being offered to implement it on their own risk - until we fully test and approve it.
Below is excerpt from the future document describing the new power management scheme for the 1.2V core:
Future Board-Level Design
• Each rail based on power-efficient Switch-Mode PS topology,
• For 1.2V core, combines existing linear and Switch-Mode topologies (Linear-SMPS “Combo”).
Why “Combo”, not Pure Switch-Mode?
• To meet timing requirements, especially while switching between Power Modes.
Linear-SMPS “Combo” Algorithm
• 1.2V high-efficiency Switch-Mode Power Supply (SMPS) with ON/OFF feature,
• ‘SMPS switch’ (low Rds-on FET), placed between SMPS output and Vybrid core power (VDD) balls, turns ON/OFF softly,
• ‘HPREG switch’ (low Rds-on FET), placed between HPREG output (NPN ballast transistor’s emitter) and Vybrid VDD balls, turns ON/OFF softly.
Switching from HPREG to SMPS
• Vybrid powers up regular way, i.e. using HPREG (SMPS and SMPS switch disabled, HPREG switch enabled).
• With HPREG running, Vybrid enables SMPS.
• Vybrid waits until unloaded SMPS stabilizes (deterministic for specific design), then enables SMPS switch.
• Both HPREG and SMPS connected to 1.2V core (VDD) rail.
• With short delay (max. a few tens of ms), Vybrid disables HPREG switch to make VDD rail run from SMPS only.
Switching from SMPS to HPREG
• While VDD rail powered from SMPS, Vybrid enables HPREG switch.
• Both HPREG and SMPS connected to VDD rail.
• With short delay, Vybrid disables SMPS switch to make VDD rail run from HPREG only.
• Now back to regular way => no difference in entering / exiting Low-Power modes, etc.
Pros and Cons
• Vybrid powers up / down and switches between Power Modes same way as before => timing kept, etc.
• If Vybrid powers up and does not execute any heavy computations until on SMPS, transistor collector current / heat dissipation / size / board copper reduced => design cost / space reduced.
• Vybrid software needs slight modification,
• Longer boot-up process,
• Three dedicated I/Os to control SMPS, SMPS Switch, and HPREG Switch (out of 100+ total / 17 used in LPStop Mode),
• If only one I/O dedicated, glue logic required (several gates, Rs, and Cs) to implement delays (preliminary schematic can be provided),
• While switching, HPREG and SMPS overlap (both connected to VDD rail) => needs approval from IC Design team (already received – N.G.).
Please let me know your opinion.
Regards, Naoum Gitnik.
/Factory Applications Engineer/
Anyone? Can I bring an externally generated 1.2V to the VDD12_AFE pin and use the BCTRL pin to enable/disable the 1.2V switcher?
Thanks for any input.
Naoum Gitnik can you help on this case?
Big thanks for that extensive answer. I'll write some of my though, but not in any particular order:
- When I first went through the Vybrid datasheet, the external NPN caught my eye immediately. You have one of the most power efficient cores on the planet, all sorts of power saving modes and features... and then you put an LDO for 1.2V line, throwing 63% of the core power through the window. Not good.
- For the Vybrid, you need two switchers, one for the 3.3V and one for the 1.5V DDR3. There are N switching power solutions out there, namely a lot of PMICs for processors, which really don't cost (much) more that two individual switchers. Let's say you would use TPS650250, which has three switchers in it. You would use one for 3.3V, the other for the 1.5V and the third for the 1.2V. Perfect. The 2.2uH inductor is fairly smaller that the suggested NPN NJD2873T4. I know that the idea of Vybrid is that you don't need a PMIC on the PCB, but i think that in a real life application you actually do.
- Let's say that you insist that you don't need a PMIC, yet still you need to generate the 1.2V. Personally, I like the approach the AR8031 (gigabit PHY) uses; it has a built in switcher. All you need is an external inductor (small. 2.2uH) and a few capacitors. It's a cool approach, if you have only one 1.2V consumer on the PCB. If you have an FPGA also on board, you still need an extra switcher for the 1.2V. So that AR8031 internal switcher saved you nothing.
- Obviously I didn't think about the response time for the 1.2V regulator needed for switching between power modes. A simple NPN is surely much faster then a switcher. I think your suggested hybrid idea is a good one, though I have no experiences in this field.
Anyways, thanks for your help and keep up the good work,
Thanks a lot for your opinion!
I agree with your analysis and will use your ideas, especially while discussing this product with its designers.
If not a secret, are you planning to utilize our Linear-SMPS “Combo” Algorithm?
If you prefer to stay with the purely linear solution, we can offer some techniques to improve heat dissipation from the transistor in the Vybrid vicinity.
Sorry I'm so late; had to do an emergency project in between.
While the Linear-SMPS combo seems attractive I cannot help to think that it's a bit complicated; but that's probably because I don't have all the info to make that judgment. So I would like to clarify a few things first.
The Vybrid has N power modes; great. But from the VDD balls perspective, there are (probably) only two:
1. Either HPREG or LPREG are ON and the ULPREG is OFF. At that time, power is present on the VDD balls.
2. The ULPREG is ON and the other two are OFF. At that time, power at VDD balls isn't present.
Also what I've noticed is that there really isn't much difference when the Vybrid is operating on HPREG or LPREG; the only difference is the NPN base current drive capability.
If the above is TRUE, then what I would suggest is the following:
1. Use a PMIC, which generates 3.3V, 1.2V and 1.5V. All rails power up at the same time.
2. The 1.2V rail is switchable via a P-MOSFET. The BCTRL is used to controll that FET. The BCTRL isn't digital, true, but it's voltage surely is 0V when HPREG and LPREG are turned OFF and 1.3V or more when they are powered ON. That 0V to 1.3V difference is more than enough to make a switch for that P-MOSFET
OK, so now you can tell me why that won't work
I would appreciate some input on my suggestion.
I think I just shot my self in the foot there. That wouldn't work. As soon as the VDD would hit 1.25V, the BCTRL would go to 0V, shutting off the P-MOSFET. Not good.
But what I would like to try is the following. I don't plan to use any of the ultra low power modes. Basically the Vybrid would just wake-up in the LPRUN mode, switch to RUN mode and it would stay in RUN mode indefinitely. The 3.3V switcher would start and then a few msec after the 1.2V switcher, which is tied directly to the VDD balls. Would that work?
If I presumed right, that from the VDD balls stand-point-of-view, there is no difference weather Vybrid is running on LPREG or HPREG, than this method should work.
Again, I appreciate your input, and please discard the previous (bad) idea.
I am glad we are acting “in sync”, since you are actually “following in my footsteps” for both using the BCTRL output to control the external FET and the straightforward architecture with an external 1.2V source.
· Regarding the BCTRL output behavior – like you, quite quickly and using the same logic, I realized the impossibility to use it for the external FET control.
· Regarding the straightforward architecture with an external 1.2V source (even without low-power modes) – according to the feedback from the Vybrid IC design team, there might be complications with the Power-On Reset and Low-Voltage Detection blocks not designed for such operation + thorough validation of operation of all the IC blocks is mandatory for such power scheme’s changes (for all the semiconductor process variations, temperatures, voltages, noise levels, etc.), and with no guaranteed success.
Sincerely yours, Naoum Gitnik.
Thanks Naoum for the input. I think I'll choose a middle way. I'll use the default NPN solution. If I choose a good NPN transistor with a low VCEsat, I could power the collector from the same 1.5V supply as the DDR3. This should provide a good balance between efficiency and complexity.
Thanks again for your effort and preventing me from wasting time on a PCB which wouldn't work.
I am glad you are one of those people, quite rare nowadays, who understand the transistor operation theory well.
The below facts will help you select the right transistor:
So, you need a transistor with Hfe high enough for your specific application, i.e. Ic and Vce. Then, based on Hfe, you calculate Ib and can find in the Datasheet what Vbe is, and then you know how low Vce can be.
High Hfe (no need to super high one, though) does 2 important things:
The lower Vce, the more critical it is; even for 1.8V mentioned in the Datasheet, the collector-base junction is already forward-biased, but much less, and the amount of Ib "stolen" is quite low.
All this has been tested preliminarily with very positive results. and for applications not running heavy computations (= lower Ic) we could go even below Vce=0.3V but this is beyond our scope.
Finding a transistor with Hfe of 100 or even 150 is not a problem nowadays; below are some examples:
and so on...
Regarding the mutual timing of the 3.3V rail and the transistor collector voltage – based on the attached scope screenshots, to not overload the BCTRL output pin, the transistor collector voltage should appear no later than 3.3V.
Sincerely yours, Naoum Gitnik.
Try to use FETs unipolar transistor to get switcher funtions.
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