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How to calibrate the time delay on the transmission line between i.MX 6Q and DDR3

Question asked by justin wu on May 23, 2013
Latest reply on May 27, 2013 by justin wu

Dear ALL;

We all know that the transmission line will occur RLC time delay or transmission time skew. The DDR3 is very sensitive to the input signal timing.The most important thing is the transmission line between i.MX 6Q and DDR3. The impedance matching is very important. We can use the smith chart to do the impedance matching by microwave engineering.

 

I change the PCB board manufacture,but I use the same PCB layout and devices. I find the connection between i.MX 6Q and DDR3 will become unstable.The environment permeability and dielectric might be little different.

I want to know what the DQS gating meaning. How do I calculate the value on the IO DQS address 0x021b083c ,0x021b0840 ,0x021b483c,and 0x021b4840?  How do I calculate the value on the IO  Read time delay value on the IO READ calibration address 0x021b0848 and 0x021b4848? How do I calculate the value on the IO WRITE time delay value on the IO Write calibration address 0x021b0850 and 0x021b4850?

Could I use the oscilloscope and Network analyzer to calculate the transmission parameters? What transmission line parameters should I know first? How could I transfer these transmission parameters into the DDR3 calibration parameters?

 

Best Regards,

Justin Wu

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