How does one enable channel interleaving on an i.MX6DQ dual-channel LPDDR2 design? The Technical Reference Manual does not provide a specific method of enabling this mode, but does state that the i.MX6DQ supports it. The LPDDR2 Programming Aid spreadsheet (MX6Q_MMDC_LPDDR2_register_programming_aid_v0.6.xlsx), available from Freescale, generates the following script statement to enable the mode:
|//// Switch PL301_FAST2 to DDR Dual-channel mapping|
|setmem /32||0x00B00000 =||0x1|
However, that address does not respond and the interleaved behavior does not occur. I've attached the spreadsheet, filled in for our memory configuration, for reference.
There are also various LPDDR2 init files available on this website that contain a line like this to set the register at 0x00B00000, but every one of them has the line commented out.
Where can I obtain documentation that details the procedure for enabling dual-channel LPDDR2 interleaving on i.MX6DQ?