AnsweredAssumed Answered

how to bring up CSI_1 interface in parallel mode

Question asked by jun sun on May 16, 2013
Latest reply on Apr 21, 2014 by Juan Antonio Gutierrez Rosas
Branched to a new discussion

Now we meet a problem on CSI_1 interface of IPU_1. On our board CSI_1 is connected to adv7182 for video capture.

 

adv7182_HS and adv7182_VS signal are not used. and 8bit data port are connected as below

csi1 pixclk   [pin H25]                 ->               adv7182_pix_clk

csi1 data12 [pin G24]                ->               adv7182_data0

csi1 data13 [pin J22]                 ->               adv7182_data1

csi1 data14 [pin G25]                ->               adv7182_data2

csi1 data15 [pin H22]                ->               adv7182_data3

csi1 data16 [pin H23]                ->               adv7182_data4

csi1 data17 [pin F24]                 ->               adv7182_data5

csi1 data18 [pin J21]                  ->               adv7182_data6

csi1 data19 [pin F25]                 ->               adv7182_data7

                                                                          

I noticed that CSI_1 is connected to IPU_1

2013-05-17_143401.jpg

.

So I make below patch for CSI_1 interface.

 

+ mxc_iomux_set_gpr_register(1, 20, 1, 1);

static struct fsl_mxc_capture_platform_data capture_data[] = {

{

  .csi = 1,

- .ipu = 0,

+ .ipu = 1,

  .mclk_source = 0,

- .is_mipi = 1,

+ .is_mipi = 0,

  }

}

 

in file adv7182.c

 

static int adv7182_probe(struct i2c_client *client,

       adv7182_data.sen.mclk = 27000000;

        adv7182_data.sen.mclk_source = 0;

        adv7182_data.sen.i2c_client = client;

        adv7182_data.sen.streamcap.timeperframe.denominator = 30;

        adv7182_data.sen.streamcap.timeperframe.numerator = 1;

        adv7182_data.std_id = V4L2_STD_ALL;

        video_idx = ADV7182_NOT_LOCKED;

        adv7182_data.sen.pix.pixelformat = V4L2_PIX_FMT_UYVY;  /* YUV422 */

        adv7182_data.sen.pix.priv = 1;  /* 1 is used to indicate TV in */

        adv7182_data.sen.csi = 1;

        adv7182_data.sen.on = true;

……


}

static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)

{

        dev_dbg(&adv7180_data.sen.i2c_client->dev, "adv7180:ioctl_g_ifparm\n");

 

        /* Initialize structure to 0s then set any non-0 values. */

        memset(p, 0, sizeof(*p));

        p->if_type = V4L2_IF_TYPE_BT656; /* This is the only possibility. */

        p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;

        p->u.bt656.nobt_hs_inv = 0;

        p->u.bt656.bt_sync_correct = 0;

        p->u.bt656.clock_curr = 27000000;

        p->u.bt656.clock_min = 6000000;

        p->u.bt656.clock_max = 28000000;

 

        return 0;

}

But the capture can’t work when I try to run mxc_v4l2_tvin.out application. The app pop up below message

ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0

It seems that the CSI_1 can’t capture any signal from data bus especially for pix clock.

I have measured the pix clock. it works out 27mhz clock signal as our expect.

 

My question are :

1.       Do I need to configure the CSI data bus width and bit pos of LSB? how to configure this info for CSI_1 of IPU_1.

2.       Please help to check my patch above. I don’t know whether I missed any important operations.

 

aa

 

 

 

 

Outcomes