AnsweredAssumed Answered

K60 SPI Chip Select Problem ? PCS(0) not asserted in DSPI0 module

Question asked by yanam on May 14, 2013
Latest reply on Aug 2, 2013 by prajnithkumar

Hello


I am able to generate clock and data using the following code. However the chip-select is not triggered or asserted automatically. I believe I am missing something, can anyone point out.


Initialization Code:

 

SPISelectPtr = SPI0_BASE_PTR;
            // Turn on the clock
            SIM_SCGC6 |= SIM_SCGC6_DSPI0_MASK;
       
            // Select pins
            // Clock
            PORTC_PCR5 &= (~PORT_PCR_MUX_MASK);
            PORTC_PCR5 = PORT_PCR_MUX(2) | PORT_PCR_DSE_MASK | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
            // Sout
            PORTC_PCR6 &= (~PORT_PCR_MUX_MASK);
            PORTC_PCR6 = PORT_PCR_MUX(2) | PORT_PCR_DSE_MASK | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
            // Sin
            PORTC_PCR7 &= (~PORT_PCR_MUX_MASK);
            PORTC_PCR7 = PORT_PCR_MUX(2) | PORT_PCR_DSE_MASK | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
       
            //Chip Select 0
            PORTD_PCR0 &= (~PORT_PCR_MUX_MASK);
            PORTD_PCR0 = PORT_PCR_MUX(2) | PORT_PCR_DSE_MASK | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;;
       
            PORTD_PCR4 &= (~PORT_PCR_MUX_MASK);
            PORTD_PCR4 = PORT_PCR_MUX(2) | PORT_PCR_DSE_MASK | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;;

    // Select Master Mode
    // Continous Clock is disabled
    // FRZ is disabled, can be enabled later using SPI_MCR_FRZ_MASK
    SPI_MCR_REG(SPISelectPtr) = (SPI_MCR_DCONF(0) | SPI_MCR_MSTR_MASK | SPI_MCR_PCSIS(0) | SPI_MCR_PCSIS(1) | SPI_MCR_PCSIS(2)
                                | SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK);

    // Frame Size = 8
    // CPOL = 1
    // CPHA = 1
    // Delay after Transfer Prescaler value is 5
    // Baud Rate Prescaler value is 1
    SPI_CTAR_REG(SPISelectPtr, 0) = SPI_CTAR_FMSZ(8) | SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK | SPI_CTAR_PDT(2) | SPI_CTAR_BR(6);


Test Function to call byte write

 

void vTestWriteByteToSPI(uint8_t u8Data, uint8_t chip_select)
{
    SPI_MemMapPtr SPISelectPtr = SPI0_BASE_PTR;


    // Making sure no chip select beyond 0 and 1
    chip_select &= 1;
    // Write a byte with CS0
    SPI_PUSHR_REG(SPISelectPtr) = SPI_PUSHR_TXDATA(u8Data) | SPI_PUSHR_CONT_MASK | SPI_PUSHR_CTAS(0) | SPI_PUSHR_PCS(chip_select + 1);
    // Wait Until Read Flag
    while (!( SPI_SR_REG(SPISelectPtr) & SPI_SR_RFDF_MASK ));
    // Clear Read Flag
    SPI_SR_REG(SPISelectPtr) |= SPI_SR_RFDF_MASK;


}



 

I am using Freescale ARM Compiler, CodeWarrior 10.4. There are pull ups on the board for CS pins. Please help pointing out mistake if any.

Outcomes