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P2020 DDR initialisation problem

Question asked by Nikolay_Bala on May 13, 2013
Latest reply on Nov 25, 2013 by Francesco Solito

Hi, i am writing embedded program for p2020 board and have troubles with configuring ddr controller.

First i load and run startup program from default TLB0 4k entry at 0xFFFFF000, that configures CCSR as TLB1 entry 1 at 0xFF700000, L2 SRAM as TLB2 entry 2 at 0xFA000000. After that, program loaded at L2 SRAM initialises 1st DDR chip as TLB1 entry 3 at 0x0, size 256 megabytes, but when I try to access DDR memory board hangs.

 

During DDR configuration I perform these steps:

1. configuring TLB1 entry 3:

selecting TLB1 entry 3 in MAS0;

setting up valid bit and translation size 256 megabytes in MAS1;

setting up effective page number 0, write-back, non-cacheable in MAS2;

setting up real page number 0 and all permission bits in MAS3.

 

 

2. configuring CCSR DDR registers:

setting up chip select bounds from 0x000 to 0x00F (they are 12 msb's of 36-bit address);

setting up ddr memory options, such as row, column bits, timings, etc, taken from memory manufactorer datasheet;

turning on hardware calibration and waiting for complete;

enabling DDR SDRAM interface logic in DDR SDRAM control register.


3. configure local access window:

setting up base 0x0 in LAW base register

setting enabled bit, memory type DDR and size of LAW 256 megabytes.


Are this correct? Without this DDR initialisation, if I try to access configured memory window 0x00000000 - 0x0FFFFFFF rises TLB data error exception, that seems okay. But after DDR init, any access to DDR memory hangs board without any errors/exceptions. How can I find what could case a hang? Are there any way to check that  DDR controller is alive and connected by the right way?

 

Thanks &  Regards,

Nikolay

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