I was reading the documentation for MCF52254. While configuring the RAMBAR register, I do not understand the meaning of bit 5.
Address Space Masks
C/I = CPU space/interrupt acknowledge cycle mask
Also, for FLASHBAR register, is it OK to enable the Address fetch speculation (AFS) bit 6. I have read from other posts that it is creates problem when enabled and it is a bug acknowledged by Freescale.
Any help will be highly appreciated.