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Configuring RAMBAR register

Question asked by Salman Razzaq on May 9, 2013
Latest reply on May 14, 2013 by Monica Arvizu

Hi,

I was reading the documentation for MCF52254. While configuring the RAMBAR register, I do not understand the meaning of bit 5.

 

RAMBAR

 

Address Space Masks

 

C/I = CPU space/interrupt acknowledge cycle mask

 

Also, for FLASHBAR register, is it OK to enable the Address fetch speculation (AFS) bit 6. I have read from other posts that it is creates problem when enabled and it is a bug acknowledged by Freescale.

 

Any help will be highly appreciated.

 

Regards.

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