MMA8451Q - FIFO

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MMA8451Q - FIFO

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georgek
Contributor II

Hi,

I would like to ask you for help with configuration of MMA8451Q accelerometer. I need to read data at 800Hz ODR, 14 bit resolution. I'm trying to set the TRIGGER MODE to FIFO. I would like to set the accelerometer so that when watermark is reached, then the interrupt is generated.

My settings of the accelerometer is not working. Setting is as follows:

// FIFO TRIGGER MODE

iic_acc_send(IIC_ACC_ADDR_MMA8451Q, 0x2A, 0x00);// standby,800Hz,14 bit

iic_acc_send(IIC_ACC_ADDR_MMA8451Q, 0x09, 0xC8);// Triger, watermark = 8 dec

iic_acc_send(IIC_ACC_ADDR_MMA8451Q, 0x0A, 0x00);// no trig 0x00

iic_acc_send(IIC_ACC_ADDR_MMA8451Q, 0x2D, 0x40);// int_en_fifo = 1

iic_acc_send(IIC_ACC_ADDR_MMA8451Q, 0x2E, 0x40);// INT1 // 0x00 = INT2

iic_acc_send(IIC_ACC_ADDR_MMA8451Q, 0x0E, 0x02);// Set 8G - HP OFF

iic_acc_send(IIC_ACC_ADDR_MMA8451Q, 0x2A, 0x01);// active, 800Hz, 14 bit

Please can you advise me what is wrong?

I would also like to ask you how to implement the reading sequence in order to reset interrupt flag in accelerometer.

Thanks for your advice,

George

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1 Solution
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TomasVaverka
NXP TechSupport
NXP TechSupport

George,

When using the trigger mode, you need to select an event/function (tap, orientation change etc.) that triggers the FIFO. This is done by setting appropriate bits in the TRIG_CFG register.

Further you need to configure the selected function, for example if you select a tap/pulse to trigger the FIFO (TRIG_CFG = 0x08), then you have to configure all related registers (0x21 – 0x28).

Default interrupt configuration is push-pull (PP_OD = 0) and active low (IPOL = 0). If you prefer different configuration, modify these bits in the CTRL_REG3 register.

In your ISR, you should read the appropriate status register for the selected embedded function (e.g. the PULSE_SRC register when the tap event is selected) to clear function’s interrupt flag. In addition to that, the FIFO interrupt needs to be deasserted by reading out at least one sample (OUT_X_MSB and OUT_X_LSB registers).

I would recommend you to look at our AN4073, it includes useful software examples such as “Event Detection Trigger on a Tap Event to Flush the Data for Further Analysis 800 Hz ODR, 8g Mode, 8-bit data” on page 13.


I hope it helps.


Regards,

Tomas

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2 Replies
1,419 Views
TomasVaverka
NXP TechSupport
NXP TechSupport

George,

When using the trigger mode, you need to select an event/function (tap, orientation change etc.) that triggers the FIFO. This is done by setting appropriate bits in the TRIG_CFG register.

Further you need to configure the selected function, for example if you select a tap/pulse to trigger the FIFO (TRIG_CFG = 0x08), then you have to configure all related registers (0x21 – 0x28).

Default interrupt configuration is push-pull (PP_OD = 0) and active low (IPOL = 0). If you prefer different configuration, modify these bits in the CTRL_REG3 register.

In your ISR, you should read the appropriate status register for the selected embedded function (e.g. the PULSE_SRC register when the tap event is selected) to clear function’s interrupt flag. In addition to that, the FIFO interrupt needs to be deasserted by reading out at least one sample (OUT_X_MSB and OUT_X_LSB registers).

I would recommend you to look at our AN4073, it includes useful software examples such as “Event Detection Trigger on a Tap Event to Flush the Data for Further Analysis 800 Hz ODR, 8g Mode, 8-bit data” on page 13.


I hope it helps.


Regards,

Tomas

1,418 Views
mstroven
Contributor III

Gentlemen,

I have an almost-identical application.  I am trying to use the FIFO in trigger mode to capture data prior to- and after a Motion event.

I have the FIFO setup in "Trigger" mode with the Motion DSP subsystem as the trigger source.

I have the FIFO high-water mark set at 16 samples.  (ie: I'm trying to capture the 16 readings prior to the motion threshold trigger, and the 16 readings after...)

I have the interrupt controller setup to ONLY trigger on FIFO events.

Here is my question:  (when the interrupt occurs, I read the source register, and discover that the high-water flag is set, but that the FIFO is not yet full (overflow bit still not set).

What is the best way - or is it possible - to only interrupt the host when the overflow occurs?

Thanks,

-Mike

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