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Configuring ECSPI-2 port

Question asked by Emanuele Placidi on May 1, 2013
Latest reply on May 6, 2013 by Emanuele Placidi
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Hi All ,

I'm currently implementing a Linux device driver to be used with the ECSPI-2 port in slave mode.

Using an i.mx53 linux-2.6.35.3 is used as OS.

 

At this moment I'm able to access the ECSPI-2 registers set (absolute Addr 0x63FA_0000) but when the port is configured in slave mode it seems that communication in a one o one settings doesn't work.

 

I would like to ask you if we can check together my settings searching for wrong or missing configuration steps.

 

As master testing device I'm using an mbed board configured to be master with the following parameters:

CS POL active Low

spi mode 2 ( clk POL=1 clk PHA=0)

bits per burst 16 , clk at 2MHZ

It is connected with the ECSPI-2 slave port as shown below:

 

Master                Slave MX53

CLK                    CLK (J12 PIN5)

MISO                  MISO (J12 PIN7)

MOSI                  MOSI (J12 PIN9)

CS                      SS     (J12 PIN3)

 

mx53 is configured as follow:

CONREG (base+0x8):

 

0x00f02001

 

burstl=0xf chnnelSelect=0x0 spiDataRdyCtl=0x0 preDivider=0x2 postDivider=0x0

channelMode 0x0 startModeControl 0x0 initExchange 0x0 HwTriggerEnabled 0x0 spiPortEnabled 0x1

 

CONFIG REG (base + 0xc)

 

0x00011110

 

lenghtInHTmode=0x0 inactiveClkState=0x0 inactiveDataState=0x1 chipSelectPolarity=0x1

chipSelMarkBurst=0x1 clkPolarity 0x1 clkPhase 0x0

 

The Pin used for chip select is the CSI0_DAT11 gpio block 5 nr 29 configured as input

 

static struct pad_desc spi2_pads[] = {

        MX53_PAD_CSI0_D8_CSPI2_SCLK,

        MX53_PAD_CSI0_D9_CSPI2_MOSI,

        MX53_PAD_CSI0_D10_CSPI2_MISO,

        MX53_PAD_CSI0_D11__GPIO_5_29,

        /* add further gpios as chipselects */

};

I suppose that pins direction for CSI0_D[8-10] is done by the spi block when channel configuration (master / slave) is configured.

 

The master board is continuously sending the same 16bit long data , I'v checked the clk and the MOSI and both of them are valid, but when I check the STATUS register or the RXDATA register on the MX53 nothing appears, it seems the MX53 doesn't get the spi  burst.

I'v also tried using the procedure reported inside  i.MX53 Multimedia Applications Processor Reference Manual, Rev. 2, .1 , page 1052 without success, The manual reports:

Configure CONREG and CONFIG REG

Fill the TXFifo (writing 64 x 16bits value )

Wait for RXFIFO Irq (37)

Read Data from RXDATA

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