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iMX53 NAND Connections

Question asked by Corey Parcell on Apr 25, 2013
Latest reply on May 8, 2013 by Jorge Ramirez
Branched to a new discussion

I am in the middle of developing a board similar to the iMX53 QSB and am trying to hookup 4 NAND chips to the iMX53 to hopefully boot off of.


My first issue is connecting the Ready/Busy lines.  I have not been able to find an example schematic showing two or more NAND chips sharing a bus.  My NAND datasheet explains that the R/B line is designed to be shared between chips since it is open drain.  However this seems like it would slow down the bus.  The iMX would have to wait until all chips were not busy since it does not know which chips are busy, only that one or more are busy.  This makes me think that each chip would get its own Chip Enable and Ready/Busy line and share everything else.


The iMX reference manual shows 4 separate Ready/Busy inputs internal to the iMX.  But I can only find one R/B line in the IO Mux planner and only one line in the datasheet for the iMX.  Does anyone have experience connecting multiple NAND chips to the iMX.  Does anyone have an example schematic?  Are the data lines, ALE, CLE, RE, and WE all shared?  Is Ready/Busy shared between NAND Chips or does each chip get its own line?


My second issue is I noticed in the datasheet that the iMX53 can boot off of NAND flash but that it is limited to CS0.  I am planning on using Ubuntu which would not entirely fit in one NAND flash chip.  However u-boot and the boot image would fit into the first chip.  Does that allow me to get around the CS0 limitation?  Once the iMX is running u-boot can it access the remaining 3 flash chips?


Also I cannot find a definite recommendation for decoupling caps on NAND chips.  Does anyone have value for caps they have used in a working application?


Thank you for any help you can offer,