AnsweredAssumed Answered

iMX28 FEC MDC clock rate

Question asked by Matthew Hilder on Apr 24, 2013
Latest reply on May 21, 2013 by JackyAtFreescale

Hello,

 

I'm using the linux-2.6.35.3 SDK and notice in drivers/net/fec.c function fec_enet_mii_init

 

    fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1;

#ifdef CONFIG_ARCH_MXS

    /* Can't get phy(8720) ID when set to 2.5M on MX28, lower it*/

    fep->phy_speed <<= 2;

#endif

    writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);

 

This is incorrect for the iMX28 as the MDC clock rate is determined by the 151MHz bus clock and not the 50MHz fep->clk.  See page 1668 of the reference manual.  This was probably the reason why phy(8720) didn't respond until the calculated rate was divided by 4.

 

I've used

 

#ifndef CONFIG_ARCH_MXS

    /*

     * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)

     */

    fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1;

#else

    /*

     * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * (MII_SPEED + 1))

     */

    fep->phy_speed = (DIV_ROUND_UP(clk_get_rate(clk_get(&pdev->dev, "h")), 5000000)-1) << 1;

#endif

    writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);

 

 

 

I now have a 2.44MHz clock rather than the original 1.84MHz clock.

 

There is a similar mistake in fec_switch.c but I'm not using that.

 

Matt.

Outcomes