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Modifying the i.MX28 BSP for a different DDR2 Device and size

Question asked by markwilliams on Apr 22, 2013
Latest reply on Jun 2, 2015 by markwilliams
Branched to a new discussion

Hi all,

 

I am hoping someone can help me with some changes to the i.MX28 WCE BSP to support a different memory size. I have read the two application notes that are available for the i.MX51 and i.MX25 but the code structure is slightly different so I want to make sure I get it right.

 

I have used the Freescale spreadsheet to make sure my DDR2 device has the correct register settings and timings. I have also modified xldr.c to reflect the necessary changes.

 

I am trying to modify the BSP to support a 256MB (2Gbit) single chip select DDR2 device (Micron MT47H128M16RT-25E) - the default BSP setting is for 128MB.

 

I am aware that I have to make changes to image_cfg.h, image_cfg.inc, config.bib, eboot.bib and oemaddrtab_cfg.inc to support the changes. I started with oemaddrtab_cfg.inc but I am unsure of how to modify this file.

 

g_oalAddressTable

    DCD 0x90000000, 0x80000000, 1

    DCD 0x90100000, 0x60000000, 1           ; SPI NOR flash

    DCD 0x80000000, 0x40000000, 128         ; RAM image mapping

    DCD 0x88000000, 0x00000000, 1           ; On-chip RAM 

    DCD 0x00000000, 0x00000000, 0           ; Terminate table

 

If I change the RAM Image mapping line to 256MB then this will occupy 0x80000000 to 0x8FFFFFFF. I will therefore nee do move the on-chip RAM location. If I move this to 0x900000000 then I will need to move the top two sections. The very top value appears to map to the internal registers of the i.MX28 (starting at the interrupt controller) on APBH.

 

How would I adjust the above table to support 256MB? Also what changes need to be made to the other files...?

 

Thank you, Mark

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