Steve Church

Vdda on 9S08QE8CLC

Discussion created by Steve Church on Apr 19, 2013
Latest reply on Apr 19, 2013 by Steve Church

I have a microphone audio signal fed into one of the analogue inputs of this uC. The mic feeds into a preamp whose o/p goes to the uC. I have this pre-amp on a separate (lower) supply than the uC supply and so I feed this voltage to the Vrefh/Vdda pin of the uC to maintain it's full dynamic range. However when I power down the mic pre-amp (I power down all external circuits and put the uC into sSTOP3 mode) I find that there is a voltage feeding out of Vdda and powering the mic pre-amp. When all connected up this voltage is 2.0 volts. When disconnected the Vdda pin sits at 2.5 volts (uC Vdd is 3 volts). Is this to be expected? I would rather not have the uC powering other connected circuits. Am I going to have to put Vdda/Vref to Vdd and put up with a reduced dynamic range (my mic circuit is powered by a 1.8V regulator - minimum required for Vrefh/Vdda. It is an 8 bit system at present and I want to get as much fidelity out of it as I can.

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