I am working to re-layout one of our display cards due to interference issues. I have recently started working on the uP (MC9S12DG128). Reading through the design guides I have run across conflicting guidelines on how to layout the oscillator circuit. In the uP datasheet and the original hardware design guide it says to leave an 'exclusion zone' under the osc section due to stray capacitance worries. However, in more recent docs (also for the same MC9S12 family) I have found it saying that running a gnd plane under the osc is not a problem and can even be advantageous in noisy environments.
Which guideline should I go with? This PCB is mounted in a very noisy environment.