MQX 4.0 and FLEXBUS for K70

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MQX 4.0 and FLEXBUS for K70

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Microfelix
Contributor IV

I just started to use MQX 4.0 with my application written for K70 with CW10.3..

So far I have used MQX 3.8 and my application works fine.

Today I find myself writing because I have always the same problem a few months ago I pointed out that 'when I tried the MQX 3.81.

I can no longer operate the flexbus to manage a my external device that needs 8-bit data bus, a CS, a RD, a WR. I have read more than one user that has the same problem but it was never resolved.

Is there anyone who has managed to make it work, or you can get information, an example of how to handle the flexbus using MQX 4.0.

thanks

Maurizio

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BielikM
Contributor III

Hello Maurizio,

Martin Latal have god point about the cache.

You should try to turn cache off. (Call _DCACHE_DISABLE() in your app should be enough).

If your app starts working with cache disabled, you have to call correct _DCACHE_FLUSH... and _DCACHE_INVALIDATE functionality or change cache policy for FLEXBUS region to non_cacheable (by LMEM_PCCRMR &= ~(LMEM_PCCRMR_R3_MASK))

I hope it helps

Martin

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Martin_
NXP Employee
NXP Employee

Hi Maurizio,

MQX 4.0 Kinetis BSPs don't initialize Flexbus and Flexbus pins. There exists an application note for using Flexbus on Kinetis devices:

http://www.freescale.com/files/microcontrollers/doc/app_note/AN4393.pdf

and you can initialize Flexbus and pin functions either from a task or alternatively, if you wish, in the BSP startup code.

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Microfelix
Contributor IV

hello

I tried all the examples I found on the datasheet.

But does not nell'MQX 4.0.

I do not know what to do. What could be wrong.

Maurizio

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Martin_
NXP Employee
NXP Employee

Attached are two files. user_config.h is for MQX 4.0 TWR-K70F120M. Please build the MQX libs with this configuration.

"hello2" MQX 4.0 example hello.c application includes Flexbus initialization, reading and writing from to Flexbus, using non-multiplexed mode (interface with MRAM on TWR-MEM). 

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Microfelix
Contributor IV

hello

I followed to the letter your examples.

but I always have a doubt.

I send a 0xFF on the data bus.

I have a pulldown on the data bus. Then writing 0xFF I get out all pins high.

But, if I go to read, I should have 0x00. But I always get 0xFF.

I do not understand this.

On MQX 3.8 okay, I get 0x00. but on MQX 4.0 I get 0xFF.

Example:

uint_8 temp = 0;

 

   printf("\n Hello\n");

  

   InitFlexbus();

 

   *(uint_8*)(0x90000000) = 0xFF;

   temp = *(uint_8*)(0x90000000);

   printf("data at MRAM start addr: 0x%08x\n", temp);

    

   _task_block();

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Martin_
NXP Employee
NXP Employee

Maurizio,

MQX 4.0 enables system cache. For 0x90000000 it is write through. So, you read does a cache hit, the cache supplies the data back to the processor ? Try to read from an address that is not valid in the cache.


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Microfelix
Contributor IV

Hello

Sorry I'm late.

I try to change address.

With the address 0x60000000 me error MQX.

If I try with an address like:

0x90000F00 I always return the value that I wrote in the data bus.

Maurizio

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BielikM
Contributor III

Hello Maurizio,

Martin Latal have god point about the cache.

You should try to turn cache off. (Call _DCACHE_DISABLE() in your app should be enough).

If your app starts working with cache disabled, you have to call correct _DCACHE_FLUSH... and _DCACHE_INVALIDATE functionality or change cache policy for FLEXBUS region to non_cacheable (by LMEM_PCCRMR &= ~(LMEM_PCCRMR_R3_MASK))

I hope it helps

Martin

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Microfelix
Contributor IV

Thank you.

now it works

Maurizio

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Angelillo
Contributor III

Hi Maurizio / Martin,

I have the same problem with the FlexBus and Cache memory with MQX 4.0. I have a FPGA connected to FlexBus on 0x80000000 adress. Apparently, I can to write and to read in this memory area but I think that I'm accessing to cache memory. :smileysad:  Is it possible? I have tried to disable the cache memory but I don't know how to do it. In my application, I have tried _DCACHE_DISABLE and LMEM_PCCRMR &= ~(LMEM_PCCRMR_R3_MASK) but it doesn't work. :smileysad:.

Can you help me? Can you send me the source code disabling the cache memory?

Thank you very much in advance for your help!

Ángel G.

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Martin_
NXP Employee
NXP Employee

I would personally keep cache enabled for software performance, especially if you employ DDR2 SDRAM.

You can map your flexbus memory page (data accesses) to 0xA0000000. Address range 0xA0000000--0xDFFFFFFF is cache inhibited for data. Worked for me to drive TWR-LCD over Flexbus.

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Microfelix
Contributor IV

hello martin,

I also tried to change the address 0xA0000000 and I deleted "_DCACHE_DISABLE."

But, now, I had to lower the speed on the LCD because I get the visual anomalies.

Can you help me?

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Martin_
NXP Employee
NXP Employee

I have no knowledge of your application, but it sounds like your code now executes faster. All code that drives data on your display now executes faster, thanks to the enabled system cache. Maybe it needs review to match with the display timing.

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Microfelix
Contributor IV

Hello Martin,

actually gets faster.

However, lowering the clock speed, it should be better, but worse in the refresh of the display. Thus the known refresh the display.

Maurizio


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Angelillo
Contributor III

Hello Martin/Maurizio,

Thank you for your help. Apparently, now works fine but I have a doubt after to read the postRe: _mem_extend usage: Is it necessary to modify linker file or not? According to this post I shouldn't to modify the linker file and I should to extend the memory pool with _mem_extend() after to configure the flexbus. However, I have modified my .tcl and .mem files as follows. Is it correct?:

".tcl" File:

MEMORY

{

   vectorrom   (RX): ORIGIN = 0x00000000, LENGTH = 0x00000400

   cfmprotrom  (R):  ORIGIN = 0x00000400, LENGTH = 0x00000020

   rom         (RX): ORIGIN = 0x00000420, LENGTH = 0x000FFBE0  # Code + Const data  

   ram         (RW): ORIGIN = 0x70000000, LENGTH = 0x08000000  # DDR2 - RW data

  fpga           (RW): ORIGIN = 0xA0000000, LENGTH = 0x00010000  # fpga (64 KB)

   sram        (RW): ORIGIN = 0x1FFF0000, LENGTH = 0x00020000  # SRAM - RW data

   # kernel space starts after RAM variables (Location of MQX Kernel data + MQX heap)

   end_of_kd   (RW): ORIGIN = 0x77FFFFF0, LENGTH = 0x00000000

  

   # Boot stack reused by MQX Kernel data

   bstack      (RW): ORIGIN = 0x2000FA00, LENGTH = 0x00000200  # Boot stack

   end_bstack  (RW): ORIGIN = 0x2000FC00, LENGTH = 0x00000000

}

KEEP_SECTION { .vectors_rom, .vectors_ram, .cfmconfig }

SECTIONS

{

   __INTERNAL_SRAM_BASE  = 0x1FFF0000;

   __INTERNAL_SRAM_SIZE  = 0x00020000;

   __INTERNAL_FLASH_BASE = 0x00000000;

   __INTERNAL_FLASH_SIZE = 0x00100000;

   __INTERNAL_FLEXNVM_BASE = 0;

   __INTERNAL_FLEXNVM_SIZE = 0;

  

   __UNCACHED_DATA_END      = 0x2000FFF0;

  __EXTERNAL_FPGA_BASE = 0xA0000000;

   __EXTERNAL_FPGA_SIZE = 0x00010000;  

 

   __EXTERNAL_MRAM_BASE  = 0x60000000;

   __EXTERNAL_MRAM_SIZE  = 0x00080000;

   __EXTERNAL_MRAM_ROM_BASE = 0x60000000;

   __EXTERNAL_MRAM_ROM_SIZE = 0x00000000;

   __EXTERNAL_MRAM_RAM_BASE = 0x60000000;

   __EXTERNAL_MRAM_RAM_SIZE = 0x00080000;

   __EXTERNAL_DDR2_RAM_BASE = 0x70000000;

   __EXTERNAL_DDR2_RAM_SIZE = 0x08000000;

   __EXTERNAL_LCD_BASE = 0x60000000;

   __EXTERNAL_LCD_SIZE = 0x1FFFF;

   __EXTERNAL_LCD_DC_BASE = 0x60010000;

[...]

".mem" File:

[...]

usederivative "MK70F15"

//         Memory Map:

//         ----------------------------------------------------------------------

range      0x00000000 0x000FFFFF 4 ReadWrite    // 1024KB Code Flash

reserved   0x00100000 0x13FFFFFF

range      0x14000000 0x14003FFF 4 ReadWrite    // 16KB Programming accelleration RAM

reserved   0x14004000 0x1FFEFFFF

range      0x1FFF0000 0x1FFFFFFF 4 ReadWrite    // 64KB On chip SRAM (TCML)

range      0x20000000 0x2000FFFF 4 ReadWrite    // 64KB On chip SRAM (TCMU)

reserved   0x20010000 0x21FFFFFF

range      0x22000000 0x221FFFFF 4 ReadWrite    // Aliased to TCMU SRAM bitband

reserved   0x22200000 0x3FFFFFFF

reserved   0x60000000 0x6FFFFFFF

range      0x70000000 0x77FFFFFF 4 ReadWrite    // DDR2

range      0xA0000000 0xA000FFFF 4 ReadWrite    // Flexbus for FPGA

reserved   0xE0100000 0xFFFFFFFF


Thank you for your help in advance!

Ángel G.





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Martin_
NXP Employee
NXP Employee

mem file is for debugger - your change allows to open memory view, in debugger, over flexbus memory page.

Typically you don't need to modify linker, only in case you wish to map some initialized data into it.

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Microfelix
Contributor IV

I simply put in my main, in the head, _DCACHE_DISABLE ();

And as I used flexbus address 0x90000000.

To me it works

Maurizio


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Angelillo
Contributor III

Hi Maurizio,

When do you say "main", do you refer to "init_bsp.c"?

Thank you,

Ángel G.

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Microfelix
Contributor IV

no. I mean your main program.

But you set the right address?

0x90000000

Maurizio


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Microfelix
Contributor IV

Simply 0x90000000 when I write and read, I should have the signals RD and WR working. But, the signals are stationary, high WR and RD low.

Maurizio

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Microfelix
Contributor IV

Now I feel then I'll let you know.

Thanks for the time being.

Maurizio

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