USB MCF51JM128

[SecondTechCo]

I am using the freescale stack and am running the demo program.    The USB clock is set up the to use the MCGPLLSCLK for the USB clock source.  The clock initialization starts to use the external reference clock for the MCGOUT.  The last line of the clock initialization changes MCGOUT to also come from the PLL.   This should not be required as the USB gets its clock source from the PLL clock as the USB stack code sets the USB_CTRL register to use the PLL clock ( IE USB_CTRL=0x03) .  When I take out this line from the end of the clock setup, the USB stops working : The line is MCGC1 &= 0x3F;

I cant have this as my projects needs a slower clock frequency to conserve power.  I thought that is what using the PLL clock for USB enables you to do.

To complicate it a bit more the reference manual says:

7.4.8 Fixed Frequency Clock

The MCG presents the divided reference clock as MCGFFCLK for use as an additional clock source. The

MCGFFCLK frequency must be no more than 1/4 of the MCGOUT frequency to be valid. When

MCGFFCLK is valid then MCGFFCLKVALID is set to 1. When MCGFFCLK is not valid then

MCGFFCLKVALID is set to 0.

This clock is intended for use in systems which include a USB interface. It allows the MCG to supply a

48MHz clock to the USB. This same clock can be used to derive MCGOUT. Alternately, MCGOUT can

be derived from either internal or external reference clock. This allows the CPU to run at a lower frequency

(to conserve power) while the USB continues to monitor traffic.

When  I view the clock diagram and read the rest of the documentation, I dont see any ties from the MCGFFCLK to USB.  The diagram only shows to sources of USB clock - MCGOUT and MCGPLLSCLK.

Any help would be appreciated.  I need to run USB at 48 mhz and MCGOUT at much less as the manual says you can do.

[SecondTechCo]

To add to the above post, there is this statement in the manual:

MCGPLLSCLK: This clock has a direct connection to the PLL output clock (running at 48 MHz) and thus allows the user to have the flexibility to run the MCGOUT at lower frequencies to conserve.power.

So the manual says in one spot the FFCLK is used for this and it says in another spot the PLLCLK is used for this.  

What is the proper method that also works. ( IE PLL clk in the freescale stack doesn't seem to work unless the MCGOUT is also set to use the PLL clk)

[SecondTechCo · Accepted solution]

After submitting a service request, the answers were difficult to understand and the questions were not answered clearly.  However it appears, the manual is wrong about using the FFCLK for USB.  It should not be used or cannot be used for USB.  Also, while the manual says you can use the the PLL clock for USB and the External clock for the bus to conserve powers its very limited. It appears the bus cannot operate below 12 Mhz using the freescale stack or the USB wont enumerate.